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Message-ID: <CAD++jLnmbGN1riUpXGa3kuwVQh2gQ8D9GZgtnJDs2yzouvBY6Q@mail.gmail.com>
Date: Tue, 20 Jan 2026 00:53:28 +0100
From: Linus Walleij <linusw@...nel.org>
To: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Yixun Lan <dlan@...too.org>, Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
spacemit@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org
Subject: Re: [PATCH v2 3/3] riscv: dts: spacemit: modify pinctrl node in dtsi
On Thu, Jan 8, 2026 at 7:43 AM Troy Mitchell
<troy.mitchell@...ux.spacemit.com> wrote:
> Change the size of the reg register to 0x1000 to match the hardware.
> This register range covers the IO power domain's register addresses.
>
> The IO power domain registers are protected. In order to access the
> protected IO power domain registers, a valid unlock sequence must be
> performed by writing the required keys to the AIB Secure Access Register
> (ASAR).
>
> The ASAR register resides within the APBC register address space.
> A corresponding syscon property `spacemit,apbc` is added to allow
> the pinctrl driver to access this register.
>
> Signed-off-by: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
Acked-by: Linus Walleij <linusw@...nel.org>
I have applied patches 1 & 2 in the series.
Yours,
Linus Walleij
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