linux-kernel - Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

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Message-ID: <aW3NV1niX7MqDW7V@hu-qianyu-lv.qualcomm.com>
Date: Sun, 18 Jan 2026 22:21:11 -0800
From: Qiang Yu <qiang.yu@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Pankaj Patil <pankaj.patil@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
        Maulik Shah <maulik.shah@....qualcomm.com>,
        Sibi Sankar <sibi.sankar@....qualcomm.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
        Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
        Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
        Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

On Wed, Jan 14, 2026 at 02:45:14PM +0100, Konrad Dybcio wrote:
> On 1/12/26 1:22 PM, Pankaj Patil wrote:
> > Introduce the base device tree support for Glymur – Qualcomm's
> > next-generation compute SoC. The new glymur.dtsi describes the core SoC
> > components, including:
> > 
> > - CPUs and CPU topology
> > - Interrupt controller and TLMM
> > - GCC,DISPCC and RPMHCC clock controllers
> > - Reserved memory and interconnects
> > - APPS and PCIe SMMU and firmware SCM
> > - Watchdog, RPMHPD, APPS RSC and SRAM
> > - PSCI and PMU nodes
> > - QUPv3 serial engines
> > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> > - PDP0 mailbox, IPCC and AOSS
> > - Display clock controller
> > - SPMI PMIC arbiter with SPMI0/1/2 buses
> > - SMP2P nodes
> > - TSENS and thermal zones (8 instances, 92 sensors)
> 
> [...]
> 
> > +			uart22: serial@...000 {
> > +				compatible = "qcom,geni-uart";
> > +				reg = <0x0 0x00898000 0x0 0x4000>;
> > +				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
> > +				clock-names = "se";
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
> > +						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
> > +						<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > +						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
> > +				interconnect-names = "qup-core",
> > +							"qup-config";
> 
> stray \t
> 
> [...]
> 
> > +			i2c8: i2c@...000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x0 0x00a80000 0x0 0x4000>;
> > +				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> > +				clock-names = "se";
> > +				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
> > +						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
> > +						<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > +						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
> > +						<&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
> > +						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> > +				interconnect-names = "qup-core",
> > +						     "qup-config",
> > +						     "qup-memory";
> > +				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> > +				dma-names = "tx",
> > +					    "rx";
> > +				pinctrl-0 = <&qup_i2c8_data_clk>;
> > +				pinctrl-names = "default";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> 
> nit: generally we try to put an \n before status
> 
> [...]
> 
> > +			pcie4_opp_table: opp-table {
> > +				compatible = "operating-points-v2";
> > +
> > +				/* GEN 1 x1 */
> > +				opp-2500000 {
> > +					opp-hz = /bits/ 64 <2500000>;
> > +					required-opps = <&rpmhpd_opp_low_svs>;
> > +					opp-peak-kBps = <250000 1>;
> > +				};
> > +
> > +				/* GEN 1 x2 and GEN 2 x1 */
> > +				opp-5000000 {
> > +					opp-hz = /bits/ 64 <5000000>;
> > +					required-opps = <&rpmhpd_opp_low_svs>;
> > +					opp-peak-kBps = <500000 1>;
> > +				};
> 
> I see that this DT doesn't define opp-level for PCIe OPP entries - could
> you please quickly check with some PCIe folks whether that's intentional
> (there are cases where it's not necessary because the controller doesn't
> need a different vote to operate an effectively-same-bw OPP with different
> link width and gen)

You are right. Thank you for pointing it out.  We need to add opp-level.

- Qiang
> 
> [...]
> 
> > +		system-cache-controller@...00000 {
> > +			compatible = "qcom,glymur-llcc";
> > +			reg = <0x0 0x21800000 0x0 0x100000>,
> > +			      <0x0 0x21a00000 0x0 0x100000>,
> > +			      <0x0 0x21c00000 0x0 0x100000>,
> > +			      <0x0 0x21e00000 0x0 0x100000>,
> > +			      <0x0 0x22800000 0x0 0x100000>,
> > +			      <0x0 0x22a00000 0x0 0x100000>,
> > +			      <0x0 0x22c00000 0x0 0x100000>,
> > +			      <0x0 0x22e00000 0x0 0x100000>,
> > +			      <0x0 0x23800000 0x0 0x100000>,
> > +			      <0x0 0x23a00000 0x0 0x100000>,
> > +			      <0x0 0x23c00000 0x0 0x100000>,
> > +			      <0x0 0x23e00000 0x0 0x100000>,
> > +			      <0x0 0x20400000 0x0 0x100000>,
> > +			      <0x0 0x20600000 0x0 0x100000>;
> > +
> > +			reg-names = "llcc0_base",
> 
> stray \n
> 
> Konrad