linux-kernel - Re: [PATCH 1/3] dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets

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Message-ID: <3e973c02-c804-43c1-863d-bb160108face@oss.qualcomm.com>
Date: Tue, 20 Jan 2026 22:21:52 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Konrad Dybcio <konradybcio@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Taniya Das <quic_tdas@...cinc.com>,
        cros-qcom-dts-watchers@...omium.org,
        Kalyan Thota
 <quic_kalyant@...cinc.com>,
        Douglas Anderson <dianders@...omium.org>,
        Harigovindan P <harigovi@...eaurora.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH 1/3] dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS
 resets



On 1/20/2026 4:49 PM, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> The MDSS resets have so far been left undescribed. Fix that.
> 
> Fixes: 75616da71291 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
>  include/dt-bindings/clock/qcom,dispcc-sc7180.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
> index b9b51617a335..070510306074 100644
> --- a/include/dt-bindings/clock/qcom,dispcc-sc7180.h
> +++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
> @@ -6,6 +6,7 @@
>  #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
>  #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
>  
> +/* Clocks */
>  #define DISP_CC_PLL0				0
>  #define DISP_CC_PLL0_OUT_EVEN			1
>  #define DISP_CC_MDSS_AHB_CLK			2
> @@ -40,7 +41,11 @@
>  #define DISP_CC_MDSS_VSYNC_CLK_SRC		31
>  #define DISP_CC_XO_CLK				32
>  
> -/* DISP_CC GDSCR */
> +/* Resets */
> +#define DISP_CC_MDSS_CORE_BCR			0
> +#define DISP_CC_MDSS_RSCC_BCR			1
> +
> +/* GDSCs */
>  #define MDSS_GDSC				0
>  
>  #endif
> 

Reviewed-by: Taniya Das <taniya.das@....qualcomm.com>

-- 
Thanks,
Taniya Das