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Message-Id: <20260119-ssqosid-cbqri-v1-2-aa2a75153832@kernel.org>
Date: Mon, 19 Jan 2026 20:14:39 -0800
From: Drew Fustini <fustini@...nel.org>
To: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Radim Krčmář <rkrcmar@...tanamicro.com>,
Samuel Holland <samuel.holland@...ive.com>,
Adrien Ricciardi <aricciardi@...libre.com>,
Nicolas Pitre <npitre@...libre.com>,
Kornel Dulęba <mindal@...ihalf.com>,
Atish Patra <atish.patra@...ux.dev>,
Atish Kumar Patra <atishp@...osinc.com>,
Vasudevan Srinivasan <vasu@...osinc.com>, Ved Shanbhogue <ved@...osinc.com>,
yunhui cui <cuiyunhui@...edance.com>, Chen Pei <cp0613@...ux.alibaba.com>,
Liu Zhiwei <zhiwei_liu@...ux.alibaba.com>, Weiwei Li <liwei1518@...il.com>,
guo.wenjia23@....com.cn, liu.qingtao2@....com.cn,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Reinette Chatre <reinette.chatre@...el.com>,
Tony Luck <tony.luck@...el.com>, Babu Moger <babu.moger@....com>,
Peter Newman <peternewman@...gle.com>, Fenghua Yu <fenghua.yu@...el.com>,
James Morse <james.morse@....com>, Ben Horgan <ben.horgan@....com>,
Dave Martin <Dave.Martin@....com>, Drew Fustini <fustini@...nel.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, x86@...nel.org
Subject: [PATCH RFC 02/19] RISC-V: Detect the Ssqosid extension
Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification
which defines the Supervisor Resource Management Configuration (srmcfg)
register.
Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Signed-off-by: Kornel Dulęba <mindal@...ihalf.com>
[fustini: rebase on riscv/for-next]
Signed-off-by: Drew Fustini <fustini@...nel.org>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4369a2338541..28dff8233b34 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -110,6 +110,7 @@
#define RISCV_ISA_EXT_ZALASR 101
#define RISCV_ISA_EXT_ZILSD 102
#define RISCV_ISA_EXT_ZCLSD 103
+#define RISCV_ISA_EXT_SSQOSID 104
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c05b11596c19..bf704b48679c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -558,6 +558,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+ __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
--
2.43.0
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