linux-kernel - [PATCH NFU RFC 18/19] riscv: dts: qemu: add CBQRI controller nodes

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Message-Id: <20260119-ssqosid-cbqri-v1-18-aa2a75153832@kernel.org>
Date: Mon, 19 Jan 2026 20:14:55 -0800
From: Drew Fustini <fustini@...nel.org>
To: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, 
 Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, 
 Radim Krčmář <rkrcmar@...tanamicro.com>, 
 Samuel Holland <samuel.holland@...ive.com>, 
 Adrien Ricciardi <aricciardi@...libre.com>, 
 Nicolas Pitre <npitre@...libre.com>, 
 Kornel Dulęba <mindal@...ihalf.com>, 
 Atish Patra <atish.patra@...ux.dev>, 
 Atish Kumar Patra <atishp@...osinc.com>, 
 Vasudevan Srinivasan <vasu@...osinc.com>, Ved Shanbhogue <ved@...osinc.com>, 
 yunhui cui <cuiyunhui@...edance.com>, Chen Pei <cp0613@...ux.alibaba.com>, 
 Liu Zhiwei <zhiwei_liu@...ux.alibaba.com>, Weiwei Li <liwei1518@...il.com>, 
 guo.wenjia23@....com.cn, liu.qingtao2@....com.cn, 
 Conor Dooley <conor+dt@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh+dt@...nel.org>, 
 Reinette Chatre <reinette.chatre@...el.com>, 
 Tony Luck <tony.luck@...el.com>, Babu Moger <babu.moger@....com>, 
 Peter Newman <peternewman@...gle.com>, Fenghua Yu <fenghua.yu@...el.com>, 
 James Morse <james.morse@....com>, Ben Horgan <ben.horgan@....com>, 
 Dave Martin <Dave.Martin@....com>, Drew Fustini <fustini@...nel.org>, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-riscv@...ts.infradead.org, x86@...nel.org
Subject: [PATCH NFU RFC 18/19] riscv: dts: qemu: add CBQRI controller nodes

[NOT FOR UPSTREAM]

Add nodes to for CBQRI-capable cache and bandwidth controllers.

Link: https://github.com/tt-fustini/qemu/tree/b4/riscv-ssqosid-cbqri
Co-developed-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Drew Fustini <fustini@...nel.org>
---
 arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 59 ++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
index 4c6257bec42d..9f65de65f758 100644
--- a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
+++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts
@@ -395,5 +395,64 @@ pci@...00000 {
 			#interrupt-cells = <0x01>;
 			#address-cells = <0x03>;
 		};
+
+		cluster0_l2: controller@...0000 {
+			compatible = "riscv,cbqri-cache";
+			reg = <0x0 0x4820000 0x0 0x1000>; /* 4KB at 0x04820000 */
+			cache-unified;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1000>;
+			cache-size = <768000>; /* 750 KiB */
+			next-level-cache = <&shared_llc>;
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
+
+		cluster1_l2: controller@...1000 {
+			compatible = "riscv,cbqri-cache";
+			reg = <0x0 0x4821000 0x0 0x1000>; /* 4KB at 0x04821000 */
+			cache-unified;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1000>;
+			cache-size = <768000>; /* 750 KiB */
+			next-level-cache = <&shared_llc>;
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
+
+		shared_llc: controller@...b000 {
+			compatible = "riscv,cbqri-cache";
+			reg = <0x0 0x482b000 0x0 0x1000>; /* 4KB at 0x0482B000 */
+			cache-unified;
+			cache-line-size = <64>;
+			cache-level = <3>;
+			cache-sets = <4096>;
+			cache-size = <3145728>; /* 3 MiB */
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
+
+		mem0: controller@...8000 {
+			compatible = "riscv,cbqri-bandwidth";
+			reg = <0x0 0x4828000 0x0 0x1000>; /* 4KB at 0x04828000 */
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
+
+		mem1: controller@...9000 {
+			compatible = "riscv,cbqri-bandwidth";
+			reg = <0x0 0x4829000 0x0 0x1000>; /* 4KB at 0x04829000 */
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
+
+		mem2: controller@...a000 {
+			compatible = "riscv,cbqri-bandwidth";
+			reg = <0x0 0x482a000 0x0 0x1000>; /* 4KB at 0x0482A000 */
+			riscv,cbqri-rcid = <64>;
+			riscv,cbqri-mcid = <256>;
+		};
 	};
 };

-- 
2.43.0