linux-kernel - Re: [PATCH net-next 3/3] net: stmmac: Add glue layer for Spacemit K3 SoC

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Message-ID: <aW8LAFhCRWlMVemz@shell.armlinux.org.uk>
Date: Tue, 20 Jan 2026 04:56:32 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Inochi Amaoto <inochiama@...il.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Yixun Lan <dlan@...too.org>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Richard Cochran <richardcochran@...il.com>,
	Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
	Yanteng Si <siyanteng@...oftware.com.cn>,
	Yao Zi <ziyao@...root.org>,
	Vladimir Oltean <vladimir.oltean@....com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Choong Yong Liang <yong.liang.choong@...ux.intel.com>,
	Maxime Chevallier <maxime.chevallier@...tlin.com>,
	Chen-Yu Tsai <wens@...nel.org>,
	Shangjuan Wei <weishangjuan@...incomputing.com>,
	Boon Khai Ng <boon.khai.ng@...era.com>,
	Quentin Schulz <quentin.schulz@...rry.de>,
	Giuseppe Cavallaro <peppe.cavallaro@...com>,
	Jose Abreu <joabreu@...opsys.com>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org, spacemit@...ts.linux.dev,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org,
	Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH net-next 3/3] net: stmmac: Add glue layer for Spacemit K3
 SoC

On Tue, Jan 20, 2026 at 12:36:08PM +0800, Inochi Amaoto wrote:
> Adds Spacemit dwmac driver support on the Spacemit K3 SoC.

Some more information would be useful. E.g. describing why you need to
fix the RGMII mode.

> +/* ctrl register bits */
> +#define PHY_INTF_RGMII			BIT(3)
> +#define PHY_INTF_MII			BIT(4)
> +
> +#define WAKE_IRQ_EN			BIT(9)
> +#define PHY_IRQ_EN			BIT(12)
> +
> +/* dline register bits */
> +#define RGMII_RX_DLINE_EN		BIT(0)
> +#define RGMII_RX_DLINE_STEP		GENMASK(5, 4)
> +#define RGMII_RX_DLINE_CODE		GENMASK(15, 8)
> +#define RGMII_TX_DLINE_EN		BIT(16)
> +#define RGMII_TX_DLINE_STEP		GENMASK(21, 20)
> +#define RGMII_TX_DLINE_CODE		GENMASK(31, 24)
> +
> +#define MAX_DLINE_DELAY_CODE		0xff
> +
> +struct spacemit_dwmac {
> +	struct device *dev;
> +	struct clk *tx;
> +};

This structure seems unused.

> +
> +/* Note: the delay step value is at 0.1ps */
> +static const unsigned int k3_delay_step_10x[4] = {
> +	367, 493, 559, 685
> +};
> +
> +static int spacemit_dwmac_set_delay(struct regmap *apmu,
> +				    unsigned int dline_offset,
> +				    unsigned int tx_code, unsigned int tx_config,
> +				    unsigned int rx_code, unsigned int rx_config)
> +{
> +	unsigned int mask, val;
> +
> +	mask = RGMII_RX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN |
> +	       RGMII_TX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN;
> +	val = FIELD_PREP(RGMII_TX_DLINE_CODE, tx_config) |
> +	      FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN |
> +	      FIELD_PREP(RGMII_TX_DLINE_CODE, rx_config) |
> +	      FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN;

These FIELD_PREP() fields look wrong. Did you mean to use DLINE_CODE
both tx_config and tx_code, and did you mean to use TX_DLINE_CODE for
rx_config ?

> +	plat_dat->clk_tx_i = devm_clk_get_enabled(&pdev->dev, "tx");
> +	if (IS_ERR(plat_dat->clk_tx_i))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat->clk_tx_i),
> +				     "failed to get tx clock\n");

You set plat_dat->clk_tx_i, but you don't point
plat_dat->set_clk_tx_rate at anything, which means the stmmac core
does nothing with this.

Given the last two points, has RGMII mode been tested on this
hardware?

-- 
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