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Message-ID: <20260120080013.2153519-25-anup.patel@oss.qualcomm.com>
Date: Tue, 20 Jan 2026 13:30:10 +0530
From: Anup Patel <anup.patel@....qualcomm.com>
To: Paolo Bonzini <pbonzini@...hat.com>, Atish Patra <atish.patra@...ux.dev>
Cc: Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <pjw@...nel.org>,
Alexandre Ghiti <alex@...ti.fr>, Shuah Khan <shuah@...nel.org>,
Anup Patel <anup@...infault.org>,
Andrew Jones <andrew.jones@....qualcomm.com>,
kvm-riscv@...ts.infradead.org, kvm@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-kselftest@...r.kernel.org,
Anup Patel <anup.patel@....qualcomm.com>
Subject: [PATCH 24/27] RISC-V: KVM: Add ONE_REG interface for nested virtualization state
Add nested virtualization state to CORE registers of the KVM RISC-V
ONE_REG interface so that it can be updated from KVM user-space in
the same way as privileged mode.
Signed-off-by: Anup Patel <anup.patel@....qualcomm.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 504e73305343..f62eaa47745b 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -65,6 +65,7 @@ struct kvm_riscv_config {
struct kvm_riscv_core {
struct user_regs_struct regs;
unsigned long mode;
+ unsigned long virt;
};
/* Possible privilege modes for kvm_riscv_core */
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 6b16eee2c833..5f0d10beeb98 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -219,6 +219,8 @@ static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
reg_val = (cntx->sstatus & SR_SPP) ?
KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
+ else if (reg_num == KVM_REG_RISCV_CORE_REG(virt))
+ reg_val = kvm_riscv_vcpu_nested_virt(vcpu);
else
return -ENOENT;
@@ -257,6 +259,9 @@ static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
cntx->sstatus |= SR_SPP;
else
cntx->sstatus &= ~SR_SPP;
+ } else if (reg_num == KVM_REG_RISCV_CORE_REG(virt)) {
+ if (riscv_isa_extension_available(vcpu->arch.isa, h))
+ kvm_riscv_vcpu_nested_virt(vcpu) = !!reg_val;
} else
return -ENOENT;
--
2.43.0
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