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Message-ID: <fmdje7ftwna5vv5xrzt5e7hpv4juzwjurhvdzzrfeifaeyyblj@givopw2u7vmn>
Date: Tue, 20 Jan 2026 19:06:21 +0800
From: Xu Yang <xu.yang_2@....com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Frank Li <Frank.li@....com>, vkoul@...nel.org, 
	neil.armstrong@...aro.org, shawnguo@...nel.org, kernel@...gutronix.de, festevam@...il.com, 
	jun.li@....com, linux-phy@...ts.infradead.org, imx@...ts.linux.dev, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] phy: fsl-imx8mq-usb: add debugfs to access control
 register

On Fri, Jan 16, 2026 at 04:19:01PM +0100, Andrew Lunn wrote:
> On Fri, Jan 16, 2026 at 07:29:39PM +0800, Xu Yang wrote:
> > On Thu, Jan 08, 2026 at 10:43:01AM -0500, Frank Li wrote:
> > > On Thu, Jan 08, 2026 at 04:36:41PM +0800, Xu Yang wrote:
> > > > The CR port is a simple 16-bit data/address parallel port that is
> > > > provided for on-chip access to the control registers inside the
> > > > USB 3.0 femtoPHY[1].
> > > 
> > > 
> > > > While access to these registers is not required
> > > > for normal PHY operation, this interface enables you to access
> > > > some of the PHY’s diagnostic features during normal operation or
> > > > to override some basic PHY control signals.
> > > 
> > > Simple said "Export these registers by debugfs to help PHY’s diagnostic."
> > > should be enough
> > 
> > OK.
> > 
> > > 
> > > >
> > > > 3 debugfs files are created to read and write control registers,
> > > > all use hexadecimal format:
> > > > ctrl_reg_base: the register offset to write, or the start offset
> > > >                to read.
> > > > ctrl_reg_count: how many continuous registers to be read.
> > > > ctrl_reg_value: read to show the continuous registers value from
> > > >                 the offset in ctrl_reg_base, to ctrl_reg_base
> > > >                 + ctrl_reg_count - 1, one line for one register.
> > > >                 when write, override the register at ctrl_reg_base,
> > > >                 one time can only change one 16bits register.
> > > 
> > > how many regs? how about create file regNNN,
> > 
> > >From 0x0 to 0x201F.
> 
> Rather than reinvent the wheel, could you use regmap?
> 
> https://elixir.bootlin.com/linux/v6.12.1/source/drivers/base/regmap/regmap-debugfs.c#L546
> 
> Regmap should be able to provide a debugfs interface for you, no
> driver code needed.
> 
> This will also help you with the abstraction between the core generic
> part of the PHY driver and the SoC integration glue. You pass the
> regmap to the core driver, and the funny muxing through two registers
> is hidden away from the core. If the next SoC integrated uses plan
> MMIO, that SoC glue driver can instantiate an MMIO regmap.
> 
> Using regmap is a good idea for core generic drivers which can be
> integrated into SoCs in different ways. It hides the SoC details
> behind a well known API.

Thanks for your suggestion.

Using regmap is generally a good fit for reusable driver and I aggre it
helps abstract Soc-specific details.

However, the regmap defbugfs has its own limitations:
1. By default the register is read-only, add write operation require rebuild
   the kernel which make it inconvenient to debug the issue on the spot. 
   Refer to: "09c6ecd39410 regmap: Add support for writing to regmap registers
              via debugfs"

    # ls /sys/kernel/debug/regmap/2-0050/ -l
    total 0
    -r-------- 1 root root 0 Jan 20 07:45 access
    -r-------- 1 root root 0 Jan 20 07:45 name
    -r-------- 1 root root 0 Jan 20 07:45 range
    -r-------- 1 root root 0 Jan 20 07:45 registers

2. It can't randomly read specific one register with common linux commands. Besides,
   the read operation is inefficient especially when the range is a bit large because
   when you cat the register it always read and output all the registers. 

Thanks,
Xu Yang

> 
>       Andrew
> 

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