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Message-Id: <20260120-topic-7180_dispcc_bcr-v1-3-0b1b442156c3@oss.qualcomm.com>
Date: Tue, 20 Jan 2026 12:19:27 +0100
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Taniya Das <quic_tdas@...cinc.com>,
cros-qcom-dts-watchers@...omium.org, Konrad Dybcio <konradybcio@...nel.org>,
Kalyan Thota <quic_kalyant@...cinc.com>,
Douglas Anderson <dianders@...omium.org>,
Harigovindan P <harigovi@...eaurora.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Val Packett <val@...kett.cool>
Subject: [PATCH 3/3] arm64: dts: qcom: sc7180: Add missing MDSS core reset
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To make sure the core starts in a predictable state, it's useful to
first reset it.
Wire up the reset to fulfill that missing part of the HW description.
Reported-by: Val Packett <val@...kett.cool>
Fixes: a3db7ad1af49 ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 45b9864e3304..f7937fa88536 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3221,6 +3221,8 @@ mdss: display-subsystem@...0000 {
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "ahb", "core";
+ resets = <&dispcc DISPCC_MDSS_CORE_BCR>;
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
--
2.52.0
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