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Message-ID: <20260120-upstream_pinctrl-v3-2-868fbf8413b5@aspeedtech.com>
Date: Tue, 20 Jan 2026 19:43:06 +0800
From: Billy Tsai <billy_tsai@...eedtech.com>
To: Lee Jones <lee@...nel.org>, Rob Herring <robh@...nel.org>, "Krzysztof
Kozlowski" <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, "Joel
Stanley" <joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>,
"Linus Walleij" <linusw@...nel.org>, Billy Tsai <billy_tsai@...eedtech.com>,
"Bartosz Golaszewski" <brgl@...nel.org>
CC: Andrew Jeffery <andrew@...id.au>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-aspeed@...ts.ozlabs.org>,
<linux-kernel@...r.kernel.org>, <openbmc@...ts.ozlabs.org>,
<linux-gpio@...r.kernel.org>, <bmc-sw@...eedtech.com>
Subject: [PATCH v3 2/3] dt-bindings: pinctrl: aspeed: Add support for
AST27xx
Add bindings for the pin controller found in ASPEED AST27xx SoCs.
The AST2700 SoC consists of two interconnected SoC instances, each
with its own pin controller register block managed by a separate
System Control Unit (SCU).
Introduce the "aspeed,ast2700-soc0-pinctrl" compatible string to
describe the SoC0 pin controller, which is not compatible with
existing ASPEED pinctrl bindings.
The SoC1 pin controller follows a regular and predictable register
layout and can be described using an existing generic pinctrl
binding, therefore no dedicated AST2700-specific compatible string
is introduced for it.
Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>
---
.../bindings/mfd/aspeed,ast2x00-scu.yaml | 27 +++++
.../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 130 +++++++++++++++++++++
2 files changed, 157 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index ff6cf8f63cbc..7eda8fddc560 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -164,4 +164,31 @@ examples:
reg = <0x7c 0x4>, <0x150 0x8>;
};
};
+
+ - |
+ syscon@...02000 {
+ compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+ reg = <0x0 0x12c02000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x12c02000 0x1000>;
+
+ pinctrl0: pinctrl@400 {
+ compatible = "aspeed,ast2700-soc0-pinctrl";
+ reg = <0x400 0x600>;
+
+ emmc-state {
+ function = "EMMC";
+ groups = "EMMCG1";
+ };
+
+ emmcclk-driving-state {
+ pins = "AC14";
+ drive-strength = <2>;
+ };
+ };
+ };
...
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
new file mode 100644
index 000000000000..f52dfe0cb4c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC0 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@...eedtech.com>
+
+description:
+ The AST2700 features a dual-SoC architecture with two interconnected SoCs,
+ each having its own System Control Unit (SCU) for independent pin control.
+ This pin controller manages the pin multiplexing for SoC0.
+
+ The SoC0 pin controller manages pin functions including eMMC, VGA DDC,
+ dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces.
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc0-pinctrl
+
+patternProperties:
+ '-state$':
+ type: object
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - EMMC
+ - VB
+ - TSPRSTN
+ - UFSCLKI
+ - VGADDC
+ - USB3AXHD
+ - USB3AXHPD
+ - USB3AXH
+ - USB3AXHP
+ - USB3AXH2B
+ - USB3AXHP2B
+ - USB3BXHD
+ - USB3BXHPD
+ - USB3BXH
+ - USB3BXHP
+ - USB3BXH2A
+ - USB3BXHP2A
+ - USB2AXHD1
+ - USB2AXHPD1
+ - USB2AXH
+ - USB2AXHP
+ - USB2AXH2B
+ - USB2AXHP2B
+ - USB2AD1
+ - USB2AHPD0
+ - USB2AH
+ - USB2AHP
+ - USB2AD0
+ - USB2BXHD1
+ - USB2BXHPD1
+ - USB2BXH
+ - USB2BXHP
+ - USB2BXH2A
+ - USB2BXHP2A
+ - USB2BD1
+ - USB2BHPD0
+ - USB2BH
+ - USB2BHP
+ - USB2BD0
+ - JTAGPSP
+ - JTAGSSP
+ - JTAGTSP
+ - JTAGDDR
+ - JTAGUSB3A
+ - JTAGUSB3B
+ - JTAGPCIEA
+ - JTAGPCIEB
+ - JTAGM0
+ - PCIERC0PERST
+ - PCIERC1PERST
+
+ groups:
+ enum:
+ - EMMCG1
+ - EMMCG4
+ - EMMCG8
+ - EMMCWPN
+ - EMMCCDN
+ - VGADDC
+ - VB1
+ - VB0
+ - TSPRSTN
+ - UFSCLKI
+ - USB3A
+ - USB3AAP
+ - USB3ABP
+ - USB3B
+ - USB3BAP
+ - USB3BBP
+ - USB2A
+ - USB2AAP
+ - USB2ABP
+ - USB2ADAP
+ - USB2AH
+ - USB2AHAP
+ - USB2B
+ - USB2BBP
+ - USB2BAP
+ - USB2BDBP
+ - USB2BH
+ - USB2BHBP
+ - JTAG0
+ - PCIERC0PERST
+ - PCIERC1PERST
+
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ drive-strength:
+ minimum: 0
+ maximum: 15
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+
+additionalProperties: false
--
2.34.1
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