linux-kernel - Re: [PATCH 0/5] Add Aspeed G7 sgpio support

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Message-ID: <CAD++jLkSmV1kVT+c2Nk-oWMS7WPgeu2NbF0yt4SUVsTmAUjq3g@mail.gmail.com>
Date: Wed, 21 Jan 2026 13:42:31 +0100
From: Linus Walleij <linusw@...nel.org>
To: Billy Tsai <billy_tsai@...eedtech.com>
Cc: Bartosz Golaszewski <brgl@...nel.org>, Joel Stanley <joel@....id.au>, 
	Andrew Jeffery <andrew@...econstruct.com.au>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-gpio@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-aspeed@...ts.ozlabs.org, 
	linux-kernel@...r.kernel.org, Andrew Jeffery <andrew@...id.au>, devicetree@...r.kernel.org, 
	bmc-sw@...eedtech.com
Subject: Re: [PATCH 0/5] Add Aspeed G7 sgpio support

On Sat, Jan 17, 2026 at 12:17 PM Billy Tsai <billy_tsai@...eedtech.com> wrote:

> The Aspeed 7th generation SoC features two SGPIO master controllers: both
> with 256 serial inputs and outputs. The main difference from the previous
> generation is that the control logic has been updated to support
> per-pin control, allowing each pin to have its own 32-bit register for
> configuring value, interrupt type, and more.
> This patch serial also add low-level operations (llops) to abstract the
> register access for SGPIO registers making it easier to extend the driver
> to support different hardware register layouts.
>
> Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>

Changes look reasonable to me!
Reviewed-by: Linus Walleij <linusw@...nel.org>

Yours,
Linus Walleij