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Message-ID: <aXEBMWSFF4jh+pop@lizhi-Precision-Tower-5810>
Date: Wed, 21 Jan 2026 11:39:13 -0500
From: Frank Li <Frank.li@....com>
To: Devendra K Verma <devendra.verma@....com>
Cc: bhelgaas@...gle.com, mani@...nel.org, vkoul@...nel.org,
dmaengine@...r.kernel.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, michal.simek@....com
Subject: Re: [PATCH v9 0/2] Add AMD MDB Endpoint and non-LL mode Support
On Mon, Jan 19, 2026 at 02:40:07PM +0530, Devendra K Verma wrote:
> This series of patch support the following:
>
> - AMD MDB Endpoint Support, as part of this patch following are
> added:
> o AMD supported device ID and vendor ID (Xilinx)
> o AMD MDB specific driver data
> o AMD specific VSEC capabilities to retrieve the base of
> phys address of MDB side DDR
> o Logic to assign the offsets to LL and data blocks if
> more number of channels are enabled than configured
> in the given pci_data struct.
>
> - Addition of non-LL mode
> o The IP supported non-LL mode functions
> o Flexibility to choose non-LL mode via dma_slave_config
> param peripheral_config, by the client for all the vendors
> using HDMA IP.
> o Allow IP utilization if LL mode is not available
>
> Devendra K Verma (2):
> dmaengine: dw-edma: Add AMD MDB Endpoint Support
> dmaengine: dw-edma: Add non-LL mode
There are open discussion at v8. Please give me some time to reply your
email before post new version.
Frank
>
> drivers/dma/dw-edma/dw-edma-core.c | 42 ++++-
> drivers/dma/dw-edma/dw-edma-core.h | 1 +
> drivers/dma/dw-edma/dw-edma-pcie.c | 223 +++++++++++++++++++++++---
> drivers/dma/dw-edma/dw-hdma-v0-core.c | 61 ++++++-
> drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +
> include/linux/dma/edma.h | 1 +
> 6 files changed, 303 insertions(+), 26 deletions(-)
>
> --
> 2.43.0
>
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