lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <aXBlBHZIPQ6xhykE@venus>
Date: Wed, 21 Jan 2026 06:51:14 +0100
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Chaoyi Chen <kernel@...kyi.com>
Cc: Andrew Lunn <andrew@...n.ch>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Heiko Stuebner <heiko@...ech.de>, Alexey Charkov <alchark@...il.com>, 
	Shawn Lin <shawn.lin@...k-chips.com>, Chaoyi Chen <chaoyi.chen@...k-chips.com>, 
	Andy Yan <andy.yan@...k-chips.com>, Nicolas Frattaroli <nicolas.frattaroli@...labora.com>, 
	Detlev Casanova <detlev.casanova@...labora.com>, Stephen Chen <stephen@...xa.com>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/3] arm64: dts: rockchip: Change gmac phy-mode to
 rgmii-id for rk3576 board

Hi,

On Wed, Jan 21, 2026 at 11:15:45AM +0800, Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen@...k-chips.com>
> 
> According to the description in the net documentation, PHY modes
> "rgmii", "rgmii-rxid" and "rgmii-txid" modes require the clock signal
> to be delayed on the PCB.
> 
> The Rockchip platform has long used the above mentioned PHY modes and
> private delay prop to describe the internal IO delay settings of the
> chip, which is inconsistent with what is described in the documentation.
> 
> Some background, for RK3576, you can assume that:
> 
>         tx_delay_time(ns) = 0.0579 * delay_line_count + 0.105
> 
> For example, tx_delay = <0x20> means:
> 
>         time = 0.0579 * 0x20 + 0.105 ns = 1.9578 ns
> 
> Recently, Andrew has often mentioned the problem of phy mode in board
> level configuration. So let's start with the RK3576 to modify this.
> 
> Please test this series of patches, thanks.

The RTL8211F PHY driver does not use the "tx-internal-delay-ps"
property, which would require using phy_get_internal_delay(). Also
the hardware only seems to support enabling/disabling a fixed delay
of 2ns, so it cannot be implemented as far as I can tell. So unless
I missed something, this series makes no sense as-is.

My suggestion would be to add support for <rx/tx>-internal-delay-ps
to the Rockchip GMAC driver by introducing a new rk_gmac_ops
entry to translate the standard properties into register values:

int rk3576_delay_conversion(unsigned int delay_ps) {
    return (delay_ps*10 - 1050) / 579;
}

That allows using standard properties in DT instead of vendor
specific "rx_delay"/"tx_delay". This results in a much better board
description and shows how far boards derive from the the standard
2ns (which can use rgmii-id without any extra delay specification).

Greetings,

-- Sebastian

Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ