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Message-Id: <20260121071412.256215-2-kenadicanady@gmail.com>
Date: Wed, 21 Jan 2026 15:14:11 +0800
From: Nadi Ke <kenadicanady@...il.com>
To: mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
orsonzhai@...il.com,
baolin.wang@...ux.alibaba.com
Cc: zhang.lyra@...il.com,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Nadi Ke <kenadicanady@...il.com>
Subject: [PATCH v2 1/2] dt-bindings: clock: sprd: add SC9832E clock controller
The SC9832E clock architecture involves several PLLs and gates.
Some gate clocks are located within the PMU global register area.
These are modeled as part of the system controller node to reflect
the hardware layout where clock control bits are interleaved with
other system control registers.
Signed-off-by: Nadi Ke <kenadicanady@...il.com>
---
Changes in v2:
- Removed the artificial 'sprd,sc9832e-pmu-gate' child node definition.
- Added '#clock-cells' to the 'sprd,sc9832e-glbregs' node definition.
.../bindings/clock/sprd,sc9832e-clk.yaml | 182 ++++++++++++++++++
include/dt-bindings/clock/sprd,sc9832e-clk.h | 177 +++++++++++++++++
2 files changed, 359 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
create mode 100644 include/dt-bindings/clock/sprd,sc9832e-clk.h
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
new file mode 100644
index 000000000..06c09b184
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sprd,sc9832e-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc SC9832E Clock Controllers
+
+maintainers:
+ - Orson Zhai <orsonzhai@...il.com>
+ - Baolin Wang <baolin.wang7@...il.com>
+ - Chunyan Zhang <zhang.lyra@...il.com>
+ - Nadi Ke <kenadicanady@...il.com>
+
+description: |
+ Unisoc SC9832E Clock Controllers.
+
+ The SC9832E clock architecture uses a mix of independent controllers and
+ sub-nodes within a system controller.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sprd,sc9832e-glbregs
+ - const: syscon
+ - enum:
+ - sprd,sc9832e-ap-clk
+ - sprd,sc9832e-aon-clk
+ - sprd,sc9832e-apahb-gate
+ - sprd,sc9832e-aonapb-gate
+ - sprd,sc9832e-apapb-gate
+ - sprd,sc9832e-pll
+ - sprd,sc9832e-mpll
+ - sprd,sc9832e-dpll
+ - sprd,sc9832e-rpll
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+ description:
+ The input parent clock(s) phandle for this clock controller.
+
+ clock-names:
+ minItems: 1
+ maxItems: 6
+
+required:
+ - compatible
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-ap-clk
+ then:
+ required:
+ - reg
+ - clocks
+ - clock-names
+ properties:
+ clocks:
+ items:
+ - description: External 26MHz clock
+ - description: External 1MHz clock
+ clock-names:
+ items:
+ - const: ext-26m
+ - const: ext-1m
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-aon-clk
+ then:
+ required:
+ - reg
+ - clocks
+ - clock-names
+ properties:
+ clocks:
+ items:
+ - description: External 4.3MHz clock
+ - description: External 26MHz clock
+ - description: External 32kHz clock
+ - description: External 6.5MHz clock
+ - description: External 13MHz clock
+ - description: External 250kHz clock
+ clock-names:
+ items:
+ - const: ext-4m3
+ - const: ext-26m
+ - const: ext-32k
+ - const: ext-6m5
+ - const: ext-13m
+ - const: ext-250k
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - sprd,sc9832e-pll
+ - sprd,sc9832e-mpll
+ - sprd,sc9832e-dpll
+ - sprd,sc9832e-rpll
+ - sprd,sc9832e-apahb-gate
+ - sprd,sc9832e-aonapb-gate
+ - sprd,sc9832e-apapb-gate
+ then:
+ required:
+ - reg
+ - clocks
+ - clock-names
+ properties:
+ clocks:
+ items:
+ - description: External 26MHz clock
+ clock-names:
+ items:
+ - const: ext-26m
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-glbregs
+ then:
+ required:
+ - reg
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ properties:
+ "#clock-cells":
+ const: 1
+ clocks:
+ items:
+ - description: External 26MHz clock
+ clock-names:
+ items:
+ - const: ext-26m
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sprd,sc9832e-clk.h>
+
+ ap_clk: clock-controller@...00000 {
+ compatible = "sprd,sc9832e-ap-clk";
+ reg = <0x21500000 0x1000>;
+ clocks = <&ext_26m>, <&ext_1m>;
+ clock-names = "ext-26m", "ext-1m";
+ #clock-cells = <1>;
+ };
+
+ pll: clock-controller@...c0000 {
+ compatible = "sprd,sc9832e-pll";
+ reg = <0x403c0000 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+
+ pmu_controller: syscon@...b0000 {
+ compatible = "sprd,sc9832e-glbregs", "syscon";
+ reg = <0x402b0000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ };
+...
+
diff --git a/include/dt-bindings/clock/sprd,sc9832e-clk.h b/include/dt-bindings/clock/sprd,sc9832e-clk.h
new file mode 100644
index 000000000..cd0b9952b
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9832e-clk.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Unisoc SC9832E platform clocks
+ *
+ * Copyright (C) 2015 Spreadtrum, Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9832E_H_
+#define _DT_BINDINGS_CLK_SC9832E_H_
+
+#define CLK_ISPPLL_GATE 0
+#define CLK_MPLL_GATE 1
+#define CLK_DPLL_GATE 2
+#define CLK_LPLL_GATE 3
+#define CLK_GPLL_GATE 4
+
+#define CLK_TWPLL 0
+#define CLK_TWPLL_768M 1
+#define CLK_TWPLL_384M 2
+#define CLK_TWPLL_192M 3
+#define CLK_TWPLL_96M 4
+#define CLK_TWPLL_48M 5
+#define CLK_TWPLL_24M 6
+#define CLK_TWPLL_12M 7
+#define CLK_TWPLL_512M 8
+#define CLK_TWPLL_256M 9
+#define CLK_TWPLL_128M 10
+#define CLK_TWPLL_64M 11
+#define CLK_TWPLL_307M2 12
+#define CLK_TWPLL_219M4 13
+#define CLK_TWPLL_170M6 14
+#define CLK_TWPLL_153M6 15
+#define CLK_TWPLL_76M8 16
+#define CLK_TWPLL_51M2 17
+#define CLK_TWPLL_38M4 18
+#define CLK_TWPLL_19M2 19
+#define CLK_LPLL 20
+#define CLK_LPLL_409M6 21
+#define CLK_LPLL_245M76 22
+#define CLK_GPLL 23
+#define CLK_ISPPLL 24
+#define CLK_ISPPLL_468M 25
+
+#define CLK_MPLL 0
+#define CLK_MPLL_50M 1
+
+#define CLK_DPLL 0
+#define CLK_DPLL_40M 1
+
+#define CLK_AUDIO_GATE 0
+#define CLK_RPLL 1
+#define CLK_RPLL_390M 2
+#define CLK_RPLL_260M 3
+#define CLK_RPLL_195M 4
+#define CLK_RPLL_26M 5
+
+#define CLK_DSI_EB 0
+#define CLK_DISPC_EB 1
+#define CLK_VSP_EB 2
+#define CLK_GSP_EB 3
+#define CLK_OTG_EB 4
+#define CLK_DMA_PUB_EB 5
+#define CLK_CE_PUB_EB 6
+#define CLK_AHB_CKG_EB 7
+#define CLK_SDIO0_EB 8
+#define CLK_SDIO1_EB 9
+#define CLK_NANDC_EB 10
+#define CLK_EMMC_EB 11
+#define CLK_SPINLOCK_EB 12
+#define CLK_CE_EFUSE_EB 13
+#define CLK_EMMC_32K_EB 14
+#define CLK_SDIO0_32K_EB 15
+#define CLK_SDIO1_32K_EB 16
+
+#define CLK_ADC_EB 0
+#define CLK_FM_EB 1
+#define CLK_TPC_EB 2
+#define CLK_GPIO_EB 3
+#define CLK_PWM0_EB 4
+#define CLK_PWM1_EB 5
+#define CLK_PWM2_EB 6
+#define CLK_PWM3_EB 7
+#define CLK_KPD_EB 8
+#define CLK_AON_SYST_EB 9
+#define CLK_AP_SYST_EB 10
+#define CLK_AON_TMR_EB 11
+#define CLK_AP_TMR0_EB 12
+#define CLK_EFUSE_EB 13
+#define CLK_EIC_EB 14
+#define CLK_INTC_EB 15
+#define CLK_ADI_EB 16
+#define CLK_AUDIF_EB 17
+#define CLK_AUD_EB 18
+#define CLK_VBC_EB 19
+#define CLK_PIN_EB 20
+#define CLK_IPI_EB 21
+#define CLK_SPLK_EB 22
+#define CLK_AP_WDG_EB 23
+#define CLK_MM_EB 24
+#define CLK_AON_APB_CKG_EB 25
+#define CLK_GPU_EB 26
+#define CLK_CA7_TS0_EB 27
+#define CLK_CA7_DAP_EB 28
+
+#define CLK_AP_APB 0
+#define CLK_NANDC_ECC 1
+#define CLK_OTG_REF 2
+#define CLK_OTG_UTMI 3
+#define CLK_UART1 4
+#define CLK_I2C0 5
+#define CLK_I2C1 6
+#define CLK_I2C2 7
+#define CLK_I2C3 8
+#define CLK_I2C4 9
+#define CLK_SPI0 10
+#define CLK_SPI2 11
+#define CLK_HS_SPI 12
+#define CLK_IIS0 13
+#define CLK_CE 14
+#define CLK_NANDC_2X 15
+#define CLK_SDIO0_2X 16
+#define CLK_SDIO1_2X 17
+#define CLK_EMMC_2X 18
+#define CLK_VSP 19
+#define CLK_GSP 20
+#define CLK_DISPC0 21
+#define CLK_DISPC0_DPI 22
+#define CLK_DSI_RXESC 23
+#define CLK_DSI_LANEBYTE 24
+
+#define CLK_AON_APB 0
+#define CLK_ADI 1
+#define CLK_AUX0 2
+#define CLK_AUX1 3
+#define CLK_PWM0 4
+#define CLK_PWM1 5
+#define CLK_PWM2 6
+#define CLK_PWM3 7
+#define CLK_THM0 8
+#define CLK_THM1 9
+#define CLK_AUDIF 10
+#define CLK_AUD_IIS_DA0 11
+#define CLK_AUD_IIS_AD0 12
+#define CLK_CA53_DAP 13
+#define CLK_CA53_DMTCK 14
+#define CLK_CA53_TS 15
+#define CLK_DJTAG_TCK 16
+#define CLK_EMC_REF 17
+#define CLK_CSSYS 18
+#define CLK_TMR 19
+#define CLK_DSI_TEST 20
+#define CLK_SDPHY_APB 21
+#define CLK_AIO_APB 22
+#define CLK_DTCK_HW 23
+#define CLK_AP_MM 24
+#define CLK_AP_AXI 25
+#define CLK_NIC_GPU 26
+#define CLK_MM_ISP 27
+
+#define CLK_SIM0_EB 0
+#define CLK_IIS0_EB 1
+#define CLK_APB_REG_EB 2
+#define CLK_SPI0_EB 3
+#define CLK_SPI2_EB 4
+#define CLK_I2C0_EB 5
+#define CLK_I2C1_EB 6
+#define CLK_I2C2_EB 7
+#define CLK_I2C3_EB 8
+#define CLK_I2C4_EB 9
+#define CLK_UART1_EB 10
+#define CLK_SIM0_32K_EB 11
+#define CLK_INTC0_EB 12
+#define CLK_INTC1_EB 13
+#define CLK_INTC2_EB 14
+#define CLK_INTC3_EB 15
+
+#endif /* _DT_BINDINGS_CLK_SC9832E_H_ */
--
2.34.1
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