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Message-ID: <20260121085347.10368-3-marex@nabladev.com>
Date: Wed, 21 Jan 2026 09:53:21 +0100
From: Marek Vasut <marex@...ladev.com>
To: linux-arm-kernel@...ts.infradead.org
Cc: Marek Vasut <marex@...ladev.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Amelie Delaunay <amelie.delaunay@...s.st.com>,
Christoph Niedermaier <cniedermaier@...electronics.com>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Raphael Gallais-Pou <rgallaispou@...il.com>,
Rob Herring <robh@...nel.org>,
devicetree@...r.kernel.org,
kernel@...electronics.com,
linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com
Subject: [PATCH 3/3] ARM: dts: stm32: Add DT overlays for DH STM32MP13xx/STM32MP15xx DHSOM
The following DTOs are supported on STM32MP15xx DHCOM PDK2:
- DH 460-200 SRAM board in header X11
- DH 497-200 adapter card with EDT ETM0700G0EDH6 Parallel RGB panel
- DH 505-200 adapter card with Chefree CH101OLHLWH-002 LVDS panel
- DH 531-100 SPI/I2C board in header X21
- DH 531-200 SPI/I2C board in header X22
- DH 560-200 7" LCD board in header X12
- DH 638-100 mezzanine card with RPi 7" DSI panel attached on top
- DH 672-100 expansion card, which contains CAN/FD transceiver and
enables PDK2 to use one more CAN/FD interface
The following DTOs are supported on STM32MP15xx DHCOM DRC02:
- Enable configuration where the DHSOM inserted into the DRC02 has
RSI 9116 WiFi populated on the SoM and where the microSD slot on
the bottom of DRC02 must not be used.
This permits a non-default configuration of the SoM and DRC02 board
used for custom device setup with on-SoM WiFi.
The following DTOs are supported on STM32MP15xx DHCOM PicoITX:
- DH 548-200 adapter card with Multi-Inno MI0700D4T-6 7" DPI panel
- DH 553-100 adapter card with Team Source Display TST043015CMHX 4.3" DPI panel
- DH 626-100 adapter card with Chefree CH101OLHLWH-002 LVDS panel
The following DTOs are supported on STM32MP15xx DHCOR Avenger96:
- FDCAN1 on low-speed expansion X6
- FDCAN2 on low-speed expansion X6
- AT24C04 I2C EEPROM on low-speed expansion X6 I2C1
- AT24C04 I2C EEPROM on low-speed expansion X6 I2C2
- AT25AA010A SPI EEPROM on low-speed expansion X6 SPI2
- 96boards OV5640 mezzanine card with sensor connected to port J3.
- DH 644-100 mezzanine card with Orisetech OTM8009A DSI panel
- DH 644-100 mezzanine card with RPi 7" DSI panel
The following DTOs are supported on STM32MP13xx DHCOR DHSBC:
- joy-IT RB-TFT3.2-V2 240x320 SPI LCD and XPT2046 resistive touch controller
Signed-off-by: Marek Vasut <marex@...ladev.com>
---
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>
Cc: Amelie Delaunay <amelie.delaunay@...s.st.com>
Cc: Christoph Niedermaier <cniedermaier@...electronics.com>
Cc: Conor Dooley <conor+dt@...nel.org>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@...il.com>
Cc: Neil Armstrong <neil.armstrong@...aro.org>
Cc: Raphael Gallais-Pou <rgallaispou@...il.com>
Cc: Rob Herring <robh@...nel.org>
Cc: devicetree@...r.kernel.org
Cc: kernel@...electronics.com
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
Cc: linux-stm32@...md-mailman.stormreply.com
---
arch/arm/boot/dts/st/Makefile | 127 ++++++++++++++++++
...p13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso | 85 ++++++++++++
...avenger96-overlay-644-100-x6-otm8009a.dtso | 61 +++++++++
...avenger96-overlay-644-100-x6-rpi7inch.dtso | 31 +++++
...m32mp15xx-avenger96-overlay-fdcan1-x6.dtso | 10 ++
...m32mp15xx-avenger96-overlay-fdcan2-x6.dtso | 10 ++
...15xx-avenger96-overlay-i2c1-eeprom-x6.dtso | 17 +++
...15xx-avenger96-overlay-i2c2-eeprom-x6.dtso | 17 +++
...m32mp15xx-avenger96-overlay-ov5640-x7.dtso | 89 ++++++++++++
...15xx-avenger96-overlay-spi2-eeprom-x6.dtso | 24 ++++
...32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso | 10 ++
...x-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi | 75 +++++++++++
.../stm32mp15xx-dhcom-overlay-panel-dpi.dtsi | 74 ++++++++++
...mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso | 27 ++++
...mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso | 24 ++++
...-pdk2-overlay-505-200-x12-ch101olhlwh.dtso | 26 ++++
...mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso | 35 +++++
...mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso | 19 +++
...mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso | 66 +++++++++
...com-pdk2-overlay-638-100-x12-rpi7inch.dtso | 28 ++++
...mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso | 13 ++
.../boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 72 ----------
...icoitx-overlay-548-200-x2-mi0700s4t-6.dtso | 35 +++++
...oitx-overlay-553-100-x2-tst043015cmhx.dtso | 35 +++++
...icoitx-overlay-626-100-x2-ch101olhlwh.dtso | 8 ++
.../dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 6 -
...15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi | 97 +++++++++++++
27 files changed, 1043 insertions(+), 78 deletions(-)
create mode 100644 arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso
create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
index e906bf6ba0041..5d29ff125d993 100644
--- a/arch/arm/boot/dts/st/Makefile
+++ b/arch/arm/boot/dts/st/Makefile
@@ -16,6 +16,91 @@ dtb-$(CONFIG_ARCH_STI) += \
stih410-b2260.dtb \
stih418-b2199.dtb \
stih418-b2264.dtb
+
+stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2-dtbs := \
+ stm32mp135f-dhcor-dhsbc.dtb \
+ stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo
+
+stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo
+
+stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo
+
+stm32mp15xx-avenger96-overlay-fdcan1-x6-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo
+
+stm32mp15xx-avenger96-overlay-fdcan2-x6-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo
+
+stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo
+
+stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo
+
+stm32mp15xx-avenger96-overlay-ov5640-x7-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo
+
+stm32mp15xx-avenger96-overlay-spi2-eeprom-x6-dtbs := \
+ stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo
+
+stm32mp15xx-dhcom-drc02-overlay-wifi-rsi-dtbs := \
+ stm32mp153c-dhcom-drc02.dtb \
+ stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo
+
+stm32mp15xx-dhcom-pdk2-overlay-460-200-x11-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-497-200-x12-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-531-100-x21-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-531-100-x22-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-560-200-x12-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \
+
+stm32mp15xx-dhcom-pdk2-overlay-672-100-x18-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \
+
+stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6-dtbs := \
+ stm32mp157c-dhcom-picoitx.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \
+
+stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \
+
+stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
+ stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
+
dtb-$(CONFIG_ARCH_STM32) += \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
@@ -30,6 +115,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h750i-art-pi.dtb \
stm32mp133c-prihmb.dtb \
stm32mp135f-dhcor-dhsbc.dtb \
+ stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \
+ stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo \
stm32mp135f-dk.dtb \
stm32mp151a-prtt1a.dtb \
stm32mp151a-prtt1c.dtb \
@@ -39,12 +126,30 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp151c-mect1s.dtb \
stm32mp151c-plyaqm.dtb \
stm32mp153c-dhcom-drc02.dtb \
+ stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtb \
+ stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo \
stm32mp153c-dhcor-drc-compact.dtb \
stm32mp153c-lxa-fairytux2-gen1.dtb \
stm32mp153c-lxa-fairytux2-gen2.dtb \
stm32mp153c-lxa-tac-gen3.dtb \
stm32mp153c-mecio1r1.dtb \
stm32mp157a-avenger96.dtb \
+ stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtb \
+ stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo \
+ stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtb \
+ stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo \
+ stm32mp15xx-avenger96-overlay-fdcan1-x6.dtb \
+ stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo \
+ stm32mp15xx-avenger96-overlay-fdcan2-x6.dtb \
+ stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo \
+ stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtb \
+ stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo \
+ stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtb \
+ stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo \
+ stm32mp15xx-avenger96-overlay-ov5640-x7.dtb \
+ stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo \
+ stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtb \
+ stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
stm32mp157a-dk1-scmi.dtb \
@@ -56,7 +161,29 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \
+ stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtb \
+ stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \
stm32mp157c-dhcom-picoitx.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \
+ stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \
+ stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \
+ stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \
stm32mp157c-dk2.dtb \
stm32mp157c-dk2-scmi.dtb \
stm32mp157c-ed1.dtb \
diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso
new file mode 100644
index 0000000000000..3801dab141e8f
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-1 {
+ label = "KEY2";
+ linux,code = <KEY_2>;
+ gpios = <&gpiog 10 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ button-0 {
+ label = "KEY1";
+ linux,code = <KEY_1>;
+ /* IRQ bank A shared with PA1 touch controller */
+ gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "KEY3";
+ linux,code = <KEY_3>;
+ /* IRQ line 0 taken by PI0 / SoM RTC IRQ */
+ gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&m_can1 {
+ /* Collides with KEY2/PG10 KEY3/PD0 */
+ status = "disabled";
+};
+
+&m_can2 {
+ /* Collides with TP_CS/PE6 */
+ status = "disabled";
+};
+
+&usart2 {
+ /* Collides with TP_IRQ/PA1 */
+ status = "disabled";
+};
+
+&spi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpiof 3 0>, <&gpioe 0 0>;
+ status = "okay";
+
+ lcd@0 {
+ compatible = "adafruit,yx240qv29", "ilitek,ili9341";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
+ rotation = <90>;
+ };
+
+ tp@1 {
+ compatible = "ti,tsc2046";
+ reg = <1>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ pendown-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <500000>;
+ ti,pressure-max = /bits/ 16 <255>;
+ ti,x-plate-ohms = /bits/ 16 <60>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso
new file mode 100644
index 0000000000000..103a2f0cf57b0
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-dsi-supply = <®18>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
+ status = "okay";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
+<dc {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep1_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso
new file mode 100644
index 0000000000000..cde2f8f68f86b
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen: touchscreen@38 {
+ };
+
+ attiny: regulator@45 {
+ };
+};
+
+#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi"
+
+<dc {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso
new file mode 100644
index 0000000000000..a9916aa8df752
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&m_can1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso
new file mode 100644
index 0000000000000..c994ff0552272
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&m_can2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso
new file mode 100644
index 0000000000000..1edfff973a815
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso
new file mode 100644
index 0000000000000..bb3db38e3e63c
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso
new file mode 100644
index 0000000000000..3056be6cd1962
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ camera0_1v5_pwr: regulator-camera0-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-1v5-reg";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ camera0_1v8_pwr: regulator-camera0-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-1v8-reg";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera0_2v8_pwr: regulator-camera0-2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-2v8-reg";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+};
+
+&dcmi {
+ status = "okay";
+};
+
+&dcmi_0 {
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&rcc CK_MCO1>;
+ clock-names = "xclk";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mco1_pins_a>;
+ pinctrl-1 = <&mco1_sleep_pins_a>;
+ assigned-clocks = <&rcc CK_MCO1>;
+ assigned-clock-parents = <&rcc CK_HSE>;
+ assigned-clock-rates = <24000000>;
+ AVDD-supply = <&camera0_2v8_pwr>;
+ DOVDD-supply = <&camera0_1v8_pwr>;
+ DVDD-supply = <&camera0_1v5_pwr>;
+ /* GPIO-J on the Dragonboard Dual-Leopard OV5640 board */
+ powerdown-gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
+ /* GPIO-I on the Dragonboard Dual-Leopard OV5640 board */
+ reset-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>;
+ rotation = <180>;
+ status = "okay";
+
+ port {
+ ov5640_0: endpoint {
+ remote-endpoint = <&stmipi_0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&stmipi {
+ status = "okay";
+};
+
+&stmipi_0 {
+ data-lanes = <1 2>;
+ remote-endpoint = <&ov5640_0>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso
new file mode 100644
index 0000000000000..acfd25c5bbcd2
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+ cs-gpios = <&gpioi 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso
new file mode 100644
index 0000000000000..aa79f95906f8c
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&sdmmc3 {
+ broken-cd;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi
new file mode 100644
index 0000000000000..be9eb1e11ecd2
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi"
+
+&{/} {
+ lvds-encoder {
+ compatible = "onnn,fin3385", "lvds-encoder";
+ pclk-sample = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_bridge_in: endpoint {
+ remote-endpoint = <<dc_dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+&display_bl {
+ pwms = <&pwm2 3 5000000 0>;
+};
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ili251x@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <16384>;
+ touchscreen-size-y = <9600>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+<dc_dpi_out {
+ remote-endpoint = <&lvds_bridge_in>;
+};
+
+&panel {
+ compatible = "chefree,ch101olhlwh-002";
+};
+
+&panel_in {
+ remote-endpoint = <&lvds_bridge_out>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi
new file mode 100644
index 0000000000000..41229ec680cc4
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+
+&{/} {
+ display_bl: display-bl {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_panel_bl>;
+ status = "okay";
+ };
+
+ panel: panel {
+ backlight = <&display_bl>;
+ power-supply = <®_panel_bl>;
+
+ port {
+ panel_in: endpoint {
+ };
+ };
+ };
+
+ reg_panel_bl: regulator-panel-bl {
+ compatible = "regulator-fixed";
+ regulator-name = "panel_backlight";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_panel_supply>;
+ };
+
+ reg_panel_supply: regulator-panel-supply {
+ compatible = "regulator-fixed";
+ regulator-name = "panel_supply";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ };
+};
+
+&timers2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pwm2: pwm {
+ #pwm-cells = <3>;
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ timer@1 {
+ reg = <1>;
+ status = "okay";
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_b>;
+ pinctrl-1 = <<dc_sleep_pins_b>;
+ status = "okay";
+
+ port {
+ ltdc_dpi_out: endpoint {
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso
new file mode 100644
index 0000000000000..161e401f5e21b
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&fmc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ sram@3,0 {
+ compatible = "mtd-ram";
+ reg = <3 0x0 0x80000>;
+ bank-width = <2>;
+
+ /* Timing values are in nS */
+ st,fmc2-ebi-cs-mux-enable;
+ st,fmc2-ebi-cs-transaction-type = <4>;
+ st,fmc2-ebi-cs-buswidth = <16>;
+ st,fmc2-ebi-cs-address-setup-ns = <6>;
+ st,fmc2-ebi-cs-address-hold-ns = <6>;
+ st,fmc2-ebi-cs-data-setup-ns = <127>;
+ st,fmc2-ebi-cs-bus-turnaround-ns = <9>;
+ st,fmc2-ebi-cs-data-hold-ns = <9>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso
new file mode 100644
index 0000000000000..1de2445450540
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi"
+
+&display_bl {
+ pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
+};
+
+<dc_dpi_out {
+ remote-endpoint = <&panel_in>;
+};
+
+&panel {
+ compatible = "dataimage,scf0700c48ggu18";
+};
+
+&panel_in {
+ remote-endpoint = <<dc_dpi_out>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso
new file mode 100644
index 0000000000000..6ef9bcf527ad0
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi"
+
+&{/} {
+ gpio-keys-polled {
+ /* BUTTON1 GPIO-B conflicts with touchscreen reset */
+ button-1 {
+ /* Use status as /delete-node/ does not work in DTOs */
+ status = "disabled";
+ };
+ };
+
+ led {
+ /* LED7 GPIO-H conflicts with touchscreen IRQ */
+ led-2 {
+ /* Use status as /delete-node/ does not work in DTOs */
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso
new file mode 100644
index 0000000000000..ce291736abbb2
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ status = "okay";
+ cs-gpios = <&gpioz 3 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso
new file mode 100644
index 0000000000000..7e040b2d8f248
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
+
+/* SPI2 is not connected on STM32MP1 DHCOM SoM */
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso
new file mode 100644
index 0000000000000..a5cef9ba7dd2a
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi"
+
+&{/} {
+ gpio-keys {
+ /*
+ * The EXTi IRQ line 6 is shared with touchscreen IRQ,
+ * so operate button-1 as polled GPIO key.
+ */
+ button-1 {
+ /* Use status as /delete-node/ does not work in DTOs */
+ status = "disabled";
+ };
+ };
+
+ gpio-keys-polled {
+ button-1 {
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ led {
+ /* LED5 GPIO-E conflicts with touchscreen IRQ */
+ led-0 {
+ /* Use status as /delete-node/ does not work in DTOs */
+ status = "disabled";
+ };
+ };
+};
+
+&display_bl {
+ pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
+};
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */
+ interrupt-parent = <&gpioc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ };
+};
+
+<dc_dpi_out {
+ remote-endpoint = <&panel_in>;
+};
+
+&panel {
+ compatible = "edt,etm0700g0edh6";
+};
+
+&panel_in {
+ remote-endpoint = <<dc_dpi_out>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso
new file mode 100644
index 0000000000000..ee8a2d1a7b87a
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen: touchscreen@38 {
+ };
+
+ attiny: regulator@45 {
+ };
+};
+
+#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi"
+
+<dc {
+ status = "okay";
+ port {
+ ltdc_ep_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso
new file mode 100644
index 0000000000000..41e473986189b
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&m_can2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
index 5c77202ee1966..0075d93911812 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
@@ -13,15 +13,6 @@ clk_ext_audio_codec: clock-codec {
clock-frequency = <24000000>;
};
- display_bl: display-bl {
- compatible = "pwm-backlight";
- pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
- brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
- default-brightness-level = <8>;
- enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
- power-supply = <®_panel_bl>;
- };
-
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <20>;
@@ -75,7 +66,6 @@ led-0 {
label = "green:led5";
gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
- status = "disabled";
};
led-1 {
@@ -97,33 +87,6 @@ led-3 {
};
};
- panel {
- compatible = "edt,etm0700g0edh6";
- backlight = <&display_bl>;
- power-supply = <®_panel_bl>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
- reg_panel_bl: regulator-panel-bl {
- compatible = "regulator-fixed";
- regulator-name = "panel_backlight";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <®_panel_supply>;
- };
-
- reg_panel_supply: regulator-panel-supply {
- compatible = "regulator-fixed";
- regulator-name = "panel_supply";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- };
-
sound {
compatible = "audio-graph-card";
widgets = "Headphone", "Headphone Jack",
@@ -188,26 +151,6 @@ sgtl5000_rx_endpoint: endpoint@1 {
};
};
-
- touchscreen@38 {
- compatible = "edt,edt-ft5406";
- reg = <0x38>;
- interrupt-parent = <&gpioc>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
- };
-};
-
-<dc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_b>;
- pinctrl-1 = <<dc_sleep_pins_b>;
- status = "okay";
-
- port {
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
};
&sai2 {
@@ -259,21 +202,6 @@ sai2b_endpoint: endpoint {
};
};
-&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names;
- status = "okay";
- pwm2: pwm {
- pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-names = "default";
- status = "okay";
- };
- timer@1 {
- status = "okay";
- };
-};
-
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso
new file mode 100644
index 0000000000000..c462c6a08833d
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2021 Andreas Geisreiter <ageisreiter@...electronics.com>
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi"
+
+&display_bl {
+ pwms = <&pwm2 3 10000000 0>;
+};
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+<dc_dpi_out {
+ remote-endpoint = <&panel_in>;
+};
+
+&panel {
+ compatible = "multi-inno,mi0700s4t-6";
+};
+
+&panel_in {
+ remote-endpoint = <<dc_dpi_out>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso
new file mode 100644
index 0000000000000..06338b7f7b679
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi"
+
+&display_bl {
+ pwms = <&pwm2 3 10000000 0>;
+};
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+<dc_dpi_out {
+ remote-endpoint = <&panel_in>;
+};
+
+&panel {
+ compatible = "team-source-display,tst043015cmhx";
+};
+
+&panel_in {
+ remote-endpoint = <<dc_dpi_out>;
+};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso
new file mode 100644
index 0000000000000..bf5c1f6eece0d
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi"
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
index aceeff6c38ba1..85d93ddfa12a1 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
@@ -258,15 +258,9 @@ &i2c2 { /* X6 I2C2 */
&i2c4 {
stmipi: stmipi@14 {
compatible = "st,st-mipid02";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mco1_pins_a>;
- pinctrl-1 = <&mco1_sleep_pins_a>;
reg = <0x14>;
clocks = <&rcc CK_MCO1>;
clock-names = "xclk";
- assigned-clocks = <&rcc CK_MCO1>;
- assigned-clock-parents = <&rcc CK_HSE>;
- assigned-clock-rates = <24000000>;
VDDE-supply = <&v1v8>;
VDDIN-supply = <&v1v8>;
reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi
new file mode 100644
index 0000000000000..518c269a1dba1
--- /dev/null
+++ b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ panel {
+ compatible = "powertip,ph800480t013-idf02";
+ backlight = <&attiny>;
+ power-supply = <&attiny>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&bridge_out>;
+ };
+ };
+ };
+};
+
+&attiny {
+ compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x45>;
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-dsi-supply = <®18>;
+ status = "okay";
+
+ bridge@0 {
+ compatible = "toshiba,tc358762";
+ reg = <0>;
+ reset-gpios = <&attiny 0 GPIO_ACTIVE_HIGH>;
+ vddc-supply = <&attiny>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ };
+ };
+ };
+};
+
+&touchscreen {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ reset-gpios = <&attiny 1 GPIO_ACTIVE_LOW>;
+ /*
+ * Disabled, since the IRQ line is not on
+ * the FPC cable, so we cannot get touch
+ * IRQs unless its connected otherwise. In
+ * that case, add entry like this one and
+ * enable below.
+ *
+ * interrupt-parent = <&gpiog>;
+ * interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ */
+ status = "disabled";
+};
--
2.51.0
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