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Message-ID: <aXCtQA5HR60f5a9g@ryzen>
Date: Wed, 21 Jan 2026 11:41:04 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Randolph <randolph@...estech.com>
Cc: linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
bhelgaas@...gle.com, robh@...nel.org, kwilczynski@...nel.org,
lpieralisi@...nel.org, mani@...nel.org, jingoohan1@...il.com,
samuel.holland@...ive.com, Frank.Li@....com, cmirabil@...hat.com,
randolph.sklin@...il.com, tim609@...estech.com
Subject: Re: [PATCH v2] PCI: dwc: Use multiple ATU regions for large bridge
windows
On Fri, Jan 09, 2026 at 07:34:30PM +0800, Randolph wrote:
> From: Samuel Holland <samuel.holland@...ive.com>
>
> Some SoCs may allocate more address space for a bridge window than can
> be covered by a single ATU region. Allow using a larger bridge window
> by allocating multiple adjacent ATU regions.
>
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
> Reviewed-by: Frank Li <Frank.Li@....com>
> Acked-by: Charles Mirabile <cmirabil@...hat.com>
> Signed-off-by: Charles Mirabile <cmirabil@...hat.com>
> Co-developed-by: Randolph Lin <randolph@...estech.com>
> Signed-off-by: Randolph Lin <randolph@...estech.com>
> ---
Reviewed-by: Niklas Cassel <cassel@...nel.org>
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