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Message-ID: <CAD++jL=PxhVWUwAimUF19=jKUZMXJM=SisK35dLcUiSXS0tugw@mail.gmail.com>
Date: Wed, 21 Jan 2026 13:12:43 +0100
From: Linus Walleij <linusw@...nel.org>
To: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Rajendra Nayak <rajendra.nayak@....qualcomm.com>,
Pankaj Patil <pankaj.patil@....qualcomm.com>, Sibi Sankar <sibi.sankar@....qualcomm.com>,
Bjorn Andersson <bjorn.andersson@....qualcomm.com>, linux-arm-msm@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/2] pinctrl: qcom: Add Mahua TLMM support
On Tue, Jan 20, 2026 at 6:23 PM Gopikrishna Garmidi
<gopikrishna.garmidi@....qualcomm.com> wrote:
> Introduce Top Level Mode Multiplexer support for Mahua, a 12-core
> variant of Qualcomm's Glymur compute SoC.
>
> Mahua shares the same pin configuration and GPIO layout as Glymur
> but requires different PDC (Power Domain Controller) wake IRQ
> mappings for proper wake-up functionality.
>
> Changes:
> - Add DeviceTree bindings for Mahua SoC TLMM block
> - Add Mahua-specific GPIO to PDC IRQ mappings
> - Add mahua tlmm soc data
> - Enable probe time config selection based on the compatible string
>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
This v3 is properly reviewed, so patches applied!
Thanks Gopikrishna!
Yours,
Linus Walleij
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