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Message-ID: <87o6mlpz9r.fsf@bootlin.com>
Date: Thu, 22 Jan 2026 14:12:16 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>, Vaishnav Achath
<vaishnav.a@...com>, Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Hervé Codina <herve.codina@...tlin.com>, Wolfram Sang
<wsa+renesas@...g-engineering.com>, Vignesh Raghavendra
<vigneshr@...com>, Santhosh Kumar K <s-k6@...com>, Pratyush Yadav
<pratyush@...nel.org>, Pascal Eberhard <pascal.eberhard@...com>,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v3 17/17] ARM: dts: r9a06g032: Describe the QSPI controller
Hi Geert,
>>
>> + qspi0: spi@...05000 {
>> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
>> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
>> + <&sysctrl R9A06G032_HCLK_QSPI0>;
>> + clock-names = "ref", "ahb", "apb";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cdns,fifo-width = <4>;
>> + cdns,fifo-depth = <4>;
>
> These two should be dropped, as per the updates to v3 of 04/17.
Gniiiiiii -_-
I did it in the yaml example and forgot to replicate it here.
Miquèl
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