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Message-ID: <20260122152713.8311-2-clamor95@gmail.com>
Date: Thu, 22 Jan 2026 17:27:11 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Thierry Reding <treding@...dia.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Svyatoslav Ryhel <clamor95@...il.com>,
Jonas Schwöbel <jonasschwoebel@...oo.de>
Cc: devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 1/3] ARM: tegra: lg-x3: add panel and bridge nodes
Add RGB-DSI bridge and panel nodes to LG Optimus 4X and Vu device tees.
Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
---
arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 23 ++++++
arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 27 +++++++
arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 81 +++++++++++++++++++-
3 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
index c6ef0a20c19f..cc14e6dca770 100644
--- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
@@ -116,6 +116,29 @@ rmi4-f11@11 {
};
};
+ spi@...0dc00 {
+ dsi@2 {
+ /*
+ * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
+ */
+ panel@1 {
+ compatible = "jdi,dx12d100vm0eaa", "renesas,r69328";
+ reg = <1>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vcc_3v0_lcd>;
+ vddio-supply = <&iovcc_1v8_lcd>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+ };
+ };
+
memory-controller@...0f000 {
emc-timings-0 {
/* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
index e32fafc7f5e0..e300a2c49edf 100644
--- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
@@ -112,6 +112,33 @@ rmi4-f11@11 {
};
};
+ spi@...0dc00 {
+ dsi@2 {
+ /*
+ * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
+ */
+ panel@1 {
+ compatible = "koe,tx13d100vm0eaa", "renesas,r61307";
+ reg = <1>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+ renesas,gamma = <3>;
+ renesas,inversion;
+ renesas,contrast;
+
+ vcc-supply = <&vcc_3v0_lcd>;
+ iovcc-supply = <&iovcc_1v8_lcd>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+ };
+ };
+
memory-controller@...0f000 {
emc-timings-2 {
/* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
index 909260a5d0fb..d71d1d6694f8 100644
--- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
@@ -20,6 +20,8 @@ aliases {
rtc0 = &pmic;
rtc1 = "/rtc@...0e000";
+ display0 = &lcd;
+
serial0 = &uartd; /* Console */
serial1 = &uartc; /* Bluetooth */
serial2 = &uartb; /* GPS */
@@ -71,6 +73,21 @@ trustzone@...00000 {
};
};
+ host1x@...00000 {
+ lcd: dc@...00000 {
+ rgb {
+ status = "okay";
+
+ port {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
+ };
+ };
+ };
+
vde@...1a000 {
assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
@@ -1357,7 +1374,58 @@ spi@...0dc00 {
status = "okay";
spi-max-frequency = <25000000>;
- /* DSI bridge */
+ dsi@2 {
+ compatible = "solomon,ssd2825";
+ reg = <2>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi-max-frequency = <1000000>;
+
+ spi-cpha;
+ spi-cpol;
+
+ reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
+
+ dvdd-supply = <&vdd_1v2_rgb>;
+ avdd-supply = <&vdd_1v2_rgb>;
+ vddio-supply = <&vdd_1v8_vio>;
+
+ solomon,hs-zero-delay-ns = <300>;
+ solomon,hs-prep-delay-ns = <65>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN3>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
+ assigned-clock-rates = <24000000>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
+ <&tegra_car TEGRA30_CLK_EXTERN3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ data-lines = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
};
pmc@...0e400 {
@@ -1617,6 +1685,17 @@ vdd_1v8_sen: regulator-sen1v8 {
vin-supply = <&vdd_3v3_vbat>;
};
+ vdd_1v2_rgb: regulator-rgb1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v2_rgb";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_vbat>;
+ };
+
vcc_3v0_lcd: regulator-lcd3v {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
--
2.51.0
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