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Message-ID: <CAPDyKFrkEZDuMbGpfxismcx=vJkSSK_XbtB762+sUFocupT63w@mail.gmail.com>
Date: Thu, 22 Jan 2026 19:03:03 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: hehuan1@...incomputing.com
Cc: adrian.hunter@...el.com, linux-mmc@...r.kernel.org,
linux-kernel@...r.kernel.org, ningyu@...incomputing.com,
linmin@...incomputing.com, pinkesh.vaghela@...fochips.com,
xuxiang@...incomputing.com
Subject: Re: [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock
On Wed, 14 Jan 2026 at 13:21, <hehuan1@...incomputing.com> wrote:
>
> From: Huan He <hehuan1@...incomputing.com>
>
> Accessing the High-Speed registers requires the AXI clock to be enabled.
>
> Signed-off-by: Huan He <hehuan1@...incomputing.com>
Applied for fixes and by adding a fixes tag, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 51949cde0958..d795745987e3 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -1588,6 +1588,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
> {
> u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
> unsigned int val, hsp_int_status, hsp_pwr_ctrl;
> + static const char * const clk_ids[] = {"axi"};
> struct of_phandle_args args;
> struct eic7700_priv *priv;
> struct regmap *hsp_regmap;
> @@ -1605,6 +1606,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
> return ret;
> }
>
> + ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
> + ARRAY_SIZE(clk_ids), clk_ids);
> + if (ret)
> + return ret;
> +
> ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
> if (ret) {
> dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);
> --
> 2.25.1
>
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