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Message-Id: <20260122-atlantis-clocks-v2-1-c66371639e66@oss.tenstorrent.com>
Date: Thu, 22 Jan 2026 16:36:37 -0600
From: Anirudh Srinivasan <asrinivasan@....tenstorrent.com>
To: Drew Fustini <dfustini@....tenstorrent.com>,
Joel Stanley <jms@....tenstorrent.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Anirudh Srinivasan <asrinivasan@....tenstorrent.com>,
Philipp Zabel <p.zabel@...gutronix.de>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, joel@....id.au,
fustini@...nel.org, mpe@...nel.org, mpe@....tenstorrent.com,
npiggin@....tenstorrent.com, agross@...nel.org, agross@....tenstorrent.com,
bmasney@...hat.com
Subject: [PATCH v2 1/3] dt-bindings: soc: tenstorrent: Add
tenstorrent,atlantis-syscon
Document bindings for Tenstorrent Atlantis syscon that manages clocks
and resets. This syscon block is instantiated 4 times in the SoC.
This commit documents the clocks from the RCPU syscon block.
Signed-off-by: Anirudh Srinivasan <asrinivasan@....tenstorrent.com>
---
.../tenstorrent/tenstorrent,atlantis-syscon.yaml | 90 ++++++++++++++++++
MAINTAINERS | 2 +
.../clock/tenstorrent,atlantis-syscon.h | 101 +++++++++++++++++++++
3 files changed, 193 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
new file mode 100644
index 000000000000..49fbe2423be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tenstorrent Atlantis SoC Syscon
+
+maintainers:
+ - Anirudh Srinivasan <asrinivasan@....tenstorrent.com>
+
+description:
+ Multifunctional register block found in Tenstorrent Atlantis SoC whose main function
+ is to control clocks and resets. This Block is instantiated multiple times in the SoC,
+ each block controls clock and resets for a different subsystem.
+
+ RCPU syscon serves low speed IO interfaces on chip
+ PCIe syscon serves all PCIe related functions
+ HSIO syscon serves high speed IO interfaces (Ethernet, USB)
+ MM syscon serves GPU, display and video processing functions
+
+properties:
+ compatible:
+ enum:
+ - tenstorrent,atlantis-syscon-rcpu
+ - tenstorrent,atlantis-syscon-pcie
+ - tenstorrent,atlantis-syscon-mm
+ - tenstorrent,atlantis-syscon-hsio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description:
+ See <dt-bindings/clock/tenstorrent,atlantis-syscon.h> for valid indices.
+
+ "#reset-cells":
+ const: 1
+
+ tenstorrent,syscon-rcpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle reference to RCPU syscon, needed by other 3 syscons (PCIe, MM, HSIO)
+ as the control registers for the PLLs that drive these subsystems are in RCPU
+ syscon's range
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+ - "#reset-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tenstorrent,atlantis-syscon-pcie
+ - tenstorrent,atlantis-syscon-mm
+ - tenstorrent,atlantis-syscon-hsio
+ then:
+ required:
+ - tenstorrent,syscon-rcpu
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon_rcpu: system-controller@...00000 {
+ compatible = "tenstorrent,atlantis-syscon-rcpu";
+ reg = <0xa8000000 0x10000>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ syscon_hsio: system-controller@...c0000 {
+ compatible = "tenstorrent,atlantis-syscon-hsio";
+ reg = <0xe00c0000 0x500>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ tenstorrent,syscon-rcpu = <&syscon_rcpu>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index dc731d37c8fe..19a98b1fa456 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22535,7 +22535,9 @@ L: linux-riscv@...ts.infradead.org
S: Maintained
T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-syscon.yaml
F: arch/riscv/boot/dts/tenstorrent/
+F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <fustini@...nel.org>
diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
new file mode 100644
index 000000000000..053cef2b43c8
--- /dev/null
+++ b/include/dt-bindings/clock/tenstorrent,atlantis-syscon.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#ifndef _DT_BINDINGS_ATLANTIS_SYSCON_H
+#define _DT_BINDINGS_ATLANTIS_SYSCON_H
+
+/*
+ * RCPU Domain Clock IDs
+ */
+#define CLK_RCPU_PLL 0
+#define CLK_RCPU_ROOT 1
+#define CLK_RCPU_DIV2 2
+#define CLK_RCPU_DIV4 3
+#define CLK_RCPU_RTC 4
+#define CLK_SMNDMA0_ACLK 5
+#define CLK_SMNDMA1_ACLK 6
+#define CLK_WDT0_PCLK 7
+#define CLK_WDT1_PCLK 8
+#define CLK_TIMER_PCLK 9
+#define CLK_PVTC_PCLK 10
+#define CLK_PMU_PCLK 11
+#define CLK_MAILBOX_HCLK 12
+#define CLK_SEC_SPACC_HCLK 13
+#define CLK_SEC_OTP_HCLK 14
+#define CLK_TRNG_PCLK 15
+#define CLK_SEC_CRC_HCLK 16
+#define CLK_SMN_HCLK 17
+#define CLK_AHB0_HCLK 18
+#define CLK_SMN_PCLK 19
+#define CLK_SMN_CLK 20
+#define CLK_SCRATCHPAD_CLK 21
+#define CLK_RCPU_CORE_CLK 22
+#define CLK_RCPU_ROM_CLK 23
+#define CLK_OTP_LOAD_CLK 24
+#define CLK_NOC_PLL 25
+#define CLK_NOCC_CLK 26
+#define CLK_NOCC_DIV2 27
+#define CLK_NOCC_DIV4 28
+#define CLK_NOCC_RTC 29
+#define CLK_NOCC_CAN 30
+#define CLK_QSPI_SCLK 31
+#define CLK_QSPI_HCLK 32
+#define CLK_I2C0_PCLK 33
+#define CLK_I2C1_PCLK 34
+#define CLK_I2C2_PCLK 35
+#define CLK_I2C3_PCLK 36
+#define CLK_I2C4_PCLK 37
+#define CLK_UART0_PCLK 38
+#define CLK_UART1_PCLK 39
+#define CLK_UART2_PCLK 40
+#define CLK_UART3_PCLK 41
+#define CLK_UART4_PCLK 42
+#define CLK_SPI0_PCLK 43
+#define CLK_SPI1_PCLK 44
+#define CLK_SPI2_PCLK 45
+#define CLK_SPI3_PCLK 46
+#define CLK_GPIO_PCLK 47
+#define CLK_CAN0_HCLK 48
+#define CLK_CAN0_CLK 49
+#define CLK_CAN1_HCLK 50
+#define CLK_CAN1_CLK 51
+#define CLK_CAN0_TIMER_CLK 52
+#define CLK_CAN1_TIMER_CLK 53
+
+/* RCPU domain reset */
+#define RST_SMNDMA0 0
+#define RST_SMNDMA1 1
+#define RST_WDT0 2
+#define RST_WDT1 3
+#define RST_TMR 4
+#define RST_PVTC 5
+#define RST_PMU 6
+#define RST_MAILBOX 7
+#define RST_SPACC 8
+#define RST_OTP 9
+#define RST_TRNG 10
+#define RST_CRC 11
+#define RST_QSPI 12
+#define RST_I2C0 13
+#define RST_I2C1 14
+#define RST_I2C2 15
+#define RST_I2C3 16
+#define RST_I2C4 17
+#define RST_UART0 18
+#define RST_UART1 19
+#define RST_UART2 20
+#define RST_UART3 21
+#define RST_UART4 22
+#define RST_SPI0 23
+#define RST_SPI1 24
+#define RST_SPI2 25
+#define RST_SPI3 26
+#define RST_GPIO 27
+#define RST_CAN0 28
+#define RST_CAN1 29
+#define RST_I2S0 30
+#define RST_I2S1 31
+
+#endif /* _DT_BINDINGS_ATLANTIS_SYSCON_H */
--
2.43.0
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