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Message-ID: <d3ec2d98-eb43-4de8-a356-006f0df43c54@oss.qualcomm.com>
Date: Thu, 22 Jan 2026 12:15:17 +0530
From: Pankaj Patil <pankaj.patil@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
Maulik Shah <maulik.shah@....qualcomm.com>,
Sibi Sankar <sibi.sankar@....qualcomm.com>,
Taniya Das <taniya.das@....qualcomm.com>,
Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
Qiang Yu <qiang.yu@....qualcomm.com>,
Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: Introduce Glymur base dtsi
On 1/22/2026 6:52 AM, Dmitry Baryshkov wrote:
> On Thu, Jan 22, 2026 at 12:05:13AM +0530, Pankaj Patil wrote:
>> Introduce the base device tree support for Glymur – Qualcomm's
>> next-generation compute SoC. The new glymur.dtsi describes the core SoC
>> components, including:
>>
>> - CPUs and CPU topology
>> - Interrupt controller and TLMM
>> - GCC,DISPCC and RPMHCC clock controllers
>> - Reserved memory and interconnects
>> - APPS and PCIe SMMU and firmware SCM
>> - Watchdog, RPMHPD, APPS RSC and SRAM
>> - PSCI and PMU nodes
>> - QUPv3 serial engines
>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
>> - PDP0 mailbox, IPCC and AOSS
>> - Display clock controller
>> - SPMI PMIC arbiter with SPMI0/1/2 buses
>> - SMP2P nodes
>> - TSENS and thermal zones (8 instances, 92 sensors)
>>
>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
>>
>> Enabled PCIe controllers and associated PHY to support boot to
>> shell with nvme storage,
>> List of PCIe instances enabled:
>>
>> - PCIe3b
>> - PCIe4
>> - PCIe5
>> - PCIe6
>>
>> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
>> Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
>> Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
>> Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
>> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
>> Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
>> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
>> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
>> Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
>> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
>> Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
>> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
>> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
>> Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 6122 ++++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 107 +
>> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 +
>> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 83 +
>> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 83 +
>> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 +
>> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 +
>> 7 files changed, 6555 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> new file mode 100644
>> index 000000000000..c0ecc64202c7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +
>> + pmh0101-thermal {
>
> Why do we have PMIC thermal zones as a part of SoC DTSI?
There were comments on v3 about moving them to out of board dts,
https://lore.kernel.org/all/aUko20ORsgrlZrIn@linaro.org/
glymur-pmics.dtsi was dropped in v4, the changes were moved to glymur.dtsi
>
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0101_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmcx0102-c0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmcx0102_c_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmcx0102-d0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmcx0102-c1-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmcx0102_c_e1_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmcx0102-d1-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmcx0102_d_e1_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-f0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-h0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0110_h_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0110-f1-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0110_f_e1_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0104-i0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0104-j0-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0104_j_e0_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> +
>> + pmh0104-l1-thermal {
>> + polling-delay-passive = <100>;
>> + thermal-sensors = <&pmh0104_l_e1_temp_alarm>;
>> +
>> + trips {
>> + trip0 {
>> + temperature = <95000>;
>> + hysteresis = <0>;
>> + type = "passive";
>> + };
>> +
>> + trip1 {
>> + temperature = <115000>;
>> + hysteresis = <0>;
>> + type = "critical";
>> + };
>> + };
>> + };
>> + };
>> +};
>
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