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Message-ID: <20260122-unselfish-charming-jaguar-dfee77@quoll>
Date: Thu, 22 Jan 2026 09:01:51 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Nadi Ke <kenadicanady@...il.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, orsonzhai@...il.com,
baolin.wang@...ux.alibaba.com, zhang.lyra@...il.com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: clock: sprd: add SC9832E clock
controller
On Wed, Jan 21, 2026 at 03:14:11PM +0800, Nadi Ke wrote:
> The SC9832E clock architecture involves several PLLs and gates.
> Some gate clocks are located within the PMU global register area.
> These are modeled as part of the system controller node to reflect
> the hardware layout where clock control bits are interleaved with
> other system control registers.
>
> Signed-off-by: Nadi Ke <kenadicanady@...il.com>
> ---
> Changes in v2:
> - Removed the artificial 'sprd,sc9832e-pmu-gate' child node definition.
> - Added '#clock-cells' to the 'sprd,sc9832e-glbregs' node definition.
>
> .../bindings/clock/sprd,sc9832e-clk.yaml | 182 ++++++++++++++++++
> include/dt-bindings/clock/sprd,sc9832e-clk.h | 177 +++++++++++++++++
> 2 files changed, 359 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
> create mode 100644 include/dt-bindings/clock/sprd,sc9832e-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
> new file mode 100644
> index 000000000..06c09b184
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
> @@ -0,0 +1,182 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/sprd,sc9832e-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Unisoc SC9832E Clock Controllers
> +
> +maintainers:
> + - Orson Zhai <orsonzhai@...il.com>
> + - Baolin Wang <baolin.wang7@...il.com>
> + - Chunyan Zhang <zhang.lyra@...il.com>
> + - Nadi Ke <kenadicanady@...il.com>
> +
> +description: |
> + Unisoc SC9832E Clock Controllers.
> +
> + The SC9832E clock architecture uses a mix of independent controllers and
> + sub-nodes within a system controller.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: sprd,sc9832e-glbregs
> + - const: syscon
This does not look like related to this binding and size of your
if:then: cases confirm this.
> + - enum:
> + - sprd,sc9832e-ap-clk
> + - sprd,sc9832e-aon-clk
> + - sprd,sc9832e-apahb-gate
> + - sprd,sc9832e-aonapb-gate
> + - sprd,sc9832e-apapb-gate
> + - sprd,sc9832e-pll
> + - sprd,sc9832e-mpll
> + - sprd,sc9832e-dpll
> + - sprd,sc9832e-rpll
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 6
> + description:
> + The input parent clock(s) phandle for this clock controller.
Drop description completely, redundant.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 6
> +
> +required:
> + - compatible
> + - '#clock-cells'
Don't mix style of quotes, ' or "
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: sprd,sc9832e-ap-clk
> + then:
> + required:
> + - reg
> + - clocks
> + - clock-names
So these three are required ALWAYS, so they should be placed in
top level required: block.
> + properties:
> + clocks:
> + items:
> + - description: External 26MHz clock
> + - description: External 1MHz clock
> + clock-names:
> + items:
> + - const: ext-26m
> + - const: ext-1m
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: sprd,sc9832e-aon-clk
> + then:
> + required:
> + - reg
> + - clocks
> + - clock-names
> + properties:
> + clocks:
> + items:
> + - description: External 4.3MHz clock
> + - description: External 26MHz clock
> + - description: External 32kHz clock
> + - description: External 6.5MHz clock
> + - description: External 13MHz clock
> + - description: External 250kHz clock
> + clock-names:
> + items:
> + - const: ext-4m3
> + - const: ext-26m
> + - const: ext-32k
> + - const: ext-6m5
> + - const: ext-13m
> + - const: ext-250k
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - sprd,sc9832e-pll
> + - sprd,sc9832e-mpll
> + - sprd,sc9832e-dpll
> + - sprd,sc9832e-rpll
> + - sprd,sc9832e-apahb-gate
> + - sprd,sc9832e-aonapb-gate
> + - sprd,sc9832e-apapb-gate
> + then:
> + required:
> + - reg
> + - clocks
> + - clock-names
> + properties:
> + clocks:
> + items:
> + - description: External 26MHz clock
> + clock-names:
> + items:
> + - const: ext-26m
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: sprd,sc9832e-glbregs
> + then:
> + required:
> + - reg
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + properties:
> + "#clock-cells":
> + const: 1
Pointless.
> + clocks:
> + items:
> + - description: External 26MHz clock
> + clock-names:
> + items:
> + - const: ext-26m
So this is exactly the same as other if... This is poor code still, like
you were not sure what you want to achieve here.
I suggest to slow down and look at other bindings first.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/sprd,sc9832e-clk.h>
> +
> + ap_clk: clock-controller@...00000 {
> + compatible = "sprd,sc9832e-ap-clk";
> + reg = <0x21500000 0x1000>;
> + clocks = <&ext_26m>, <&ext_1m>;
> + clock-names = "ext-26m", "ext-1m";
> + #clock-cells = <1>;
> + };
> +
> + pll: clock-controller@...c0000 {
> + compatible = "sprd,sc9832e-pll";
> + reg = <0x403c0000 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "ext-26m";
> + #clock-cells = <1>;
> + };
Drop node, same as previous one.
I did not ask to grow the examples!
> +
> + pmu_controller: syscon@...b0000 {
> + compatible = "sprd,sc9832e-glbregs", "syscon";
Drop node, same as previous one.
> + reg = <0x402b0000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_26m>;
> + clock-names = "ext-26m";
> + };
> +...
Best regards,
Krzysztof
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