linux-kernel - Re: [PATCH v2 3/3] PCI: dwc: ep: Add comment explaining controller-level PTM access

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <aXHjiSiP3If37Hln@ryzen>
Date: Thu, 22 Jan 2026 09:45:36 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Aksh Garg <a-garg7@...com>
Cc: linux-pci@...r.kernel.org, jingoohan1@...il.com, mani@...nel.org,
	lpieralisi@...nel.org, kwilczynski@...nel.org, robh@...nel.org,
	bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
	s-vadapalli@...com, danishanwar@...com
Subject: Re: [PATCH v2 3/3] PCI: dwc: ep: Add comment explaining
 controller-level PTM access

On Thu, Jan 22, 2026 at 01:55:38PM +0530, Aksh Garg wrote:
> PCIe r6.0, section 7.9.15 requires PTM capability in exactly one
> function to control all PTM-capable functions. This makes PTM registers
> controller-level rather than per-function.
> 
> As suggested by Niklas Cassel, add a comment explaining why PTM
> capability registers are accessed using the standard DBI accessors
> instead of func_no indexed per-function accessors.

Nit: I think you can remove: "As suggested by Niklas Cassel, "
and just start the sentence with:
"Add a comment explaining .."
since you already give me credit using the Suggested-by tag.


> 
> Suggested-by: Niklas Cassel <cassel@...nel.org>
> Signed-off-by: Aksh Garg <a-garg7@...com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-ep.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 12625a1059a4..0a9d5402f23a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -995,6 +995,17 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
>  	if (ep->ops->init)
>  		ep->ops->init(ep);
>  
> +	/*
> +	 * PCIe r6.0, section 7.9.15 states that for endpoints that support PTM,
> +	 * this capability structure is required in exactly one function, which
> +	 * controls the PTM behavior of all PTM capable functions. This indicates
> +	 * the PTM capability structure represents controller-level registers
> +	 * rather than per-function registers.
> +	 *
> +	 * Therefore, PTM capability registers are configured using the standard DBI
> +	 * accessors, instead of func_no indexed per-function accessors.
> +	 */
> +

Nit: don't think this empty newline is needed.

>  	ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>  
>  	/*
> -- 
> 2.34.1
> 

With nits fixed:
Reviewed-by: Niklas Cassel <cassel@...nel.org>