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Message-Id: <20260123-eliza-clocks-v1-1-664f1931f8c7@oss.qualcomm.com>
Date: Fri, 23 Jan 2026 15:37:13 +0200
From: Abel Vesa <abel.vesa@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Luca Weiss <luca.weiss@...rphone.com>,
Taniya Das <taniya.das@....qualcomm.com>,
Taniya Das <quic_tdas@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Abel Vesa <abel.vesa@....qualcomm.com>
Subject: [PATCH 1/4] dt-bindings: clock: qcom: document the Eliza Global
Clock Controller
From: Taniya Das <taniya.das@....qualcomm.com>
Add bindings documentation for the Global Clock Controller on Qualcomm
Eliza SoC.
Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@....qualcomm.com>
---
.../devicetree/bindings/clock/qcom,milos-gcc.yaml | 9 +-
include/dt-bindings/clock/qcom,eliza-gcc.h | 218 +++++++++++++++++++++
2 files changed, 225 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
index cf244c155f9a..539a0a804152 100644
--- a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
@@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@...rphone.com>
+ - Taniya Das <taniya.das@....qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Milos.
- See also: include/dt-bindings/clock/qcom,milos-gcc.h
+ See also:
+ - include/dt-bindings/clock/qcom,eliza-gcc.h
+ - include/dt-bindings/clock/qcom,milos-gcc.h
properties:
compatible:
- const: qcom,milos-gcc
+ enum:
+ - qcom,milos-gcc
+ - qcom,eliza-gcc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,eliza-gcc.h b/include/dt-bindings/clock/qcom,eliza-gcc.h
new file mode 100644
index 000000000000..3e0ff3fb69f6
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-gcc.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2
+#define GCC_BOOT_ROM_AHB_CLK 3
+#define GCC_CAM_BIST_MCLK_AHB_CLK 4
+#define GCC_CAMERA_AHB_CLK 5
+#define GCC_CAMERA_HF_AXI_CLK 6
+#define GCC_CAMERA_SF_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
+#define GCC_CNOC_PCIE_SF_AXI_CLK 11
+#define GCC_DDRSS_GPU_AXI_CLK 12
+#define GCC_DDRSS_PCIE_SF_QTB_CLK 13
+#define GCC_DISP_AHB_CLK 14
+#define GCC_DISP_HF_AXI_CLK 15
+#define GCC_GP1_CLK 16
+#define GCC_GP1_CLK_SRC 17
+#define GCC_GP2_CLK 18
+#define GCC_GP2_CLK_SRC 19
+#define GCC_GP3_CLK 20
+#define GCC_GP3_CLK_SRC 21
+#define GCC_GPLL0 22
+#define GCC_GPLL0_OUT_EVEN 23
+#define GCC_GPLL4 24
+#define GCC_GPLL7 25
+#define GCC_GPLL8 26
+#define GCC_GPLL9 27
+#define GCC_GPU_CFG_AHB_CLK 28
+#define GCC_GPU_GEMNOC_GFX_CLK 29
+#define GCC_GPU_GPLL0_CPH_CLK_SRC 30
+#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 31
+#define GCC_GPU_SMMU_VOTE_CLK 32
+#define GCC_MMU_TCU_VOTE_CLK 33
+#define GCC_PCIE_0_AUX_CLK 34
+#define GCC_PCIE_0_AUX_CLK_SRC 35
+#define GCC_PCIE_0_CFG_AHB_CLK 36
+#define GCC_PCIE_0_MSTR_AXI_CLK 37
+#define GCC_PCIE_0_PHY_RCHNG_CLK 38
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 39
+#define GCC_PCIE_0_PIPE_CLK 40
+#define GCC_PCIE_0_PIPE_CLK_SRC 41
+#define GCC_PCIE_0_PIPE_DIV2_CLK 42
+#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 43
+#define GCC_PCIE_0_SLV_AXI_CLK 44
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
+#define GCC_PCIE_1_AUX_CLK 46
+#define GCC_PCIE_1_AUX_CLK_SRC 47
+#define GCC_PCIE_1_CFG_AHB_CLK 48
+#define GCC_PCIE_1_MSTR_AXI_CLK 49
+#define GCC_PCIE_1_PHY_RCHNG_CLK 50
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51
+#define GCC_PCIE_1_PIPE_CLK 52
+#define GCC_PCIE_1_PIPE_CLK_SRC 53
+#define GCC_PCIE_1_PIPE_DIV2_CLK 54
+#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 55
+#define GCC_PCIE_1_SLV_AXI_CLK 56
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57
+#define GCC_PCIE_RSCC_CFG_AHB_CLK 58
+#define GCC_PCIE_RSCC_XO_CLK 59
+#define GCC_PDM2_CLK 60
+#define GCC_PDM2_CLK_SRC 61
+#define GCC_PDM_AHB_CLK 62
+#define GCC_PDM_XO4_CLK 63
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK 64
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 66
+#define GCC_QMIP_GPU_AHB_CLK 67
+#define GCC_QMIP_PCIE_AHB_CLK 68
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 71
+#define GCC_QUPV3_WRAP1_CORE_CLK 72
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 73
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 74
+#define GCC_QUPV3_WRAP1_S0_CLK 75
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 76
+#define GCC_QUPV3_WRAP1_S1_CLK 77
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 78
+#define GCC_QUPV3_WRAP1_S2_CLK 79
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 80
+#define GCC_QUPV3_WRAP1_S3_CLK 81
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 82
+#define GCC_QUPV3_WRAP1_S4_CLK 83
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 84
+#define GCC_QUPV3_WRAP1_S5_CLK 85
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 86
+#define GCC_QUPV3_WRAP1_S6_CLK 87
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 88
+#define GCC_QUPV3_WRAP1_S7_CLK 89
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 90
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 91
+#define GCC_QUPV3_WRAP2_CORE_CLK 92
+#define GCC_QUPV3_WRAP2_S0_CLK 93
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 94
+#define GCC_QUPV3_WRAP2_S1_CLK 95
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 96
+#define GCC_QUPV3_WRAP2_S2_CLK 97
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 98
+#define GCC_QUPV3_WRAP2_S3_CLK 99
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 100
+#define GCC_QUPV3_WRAP2_S4_CLK 101
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 102
+#define GCC_QUPV3_WRAP2_S5_CLK 103
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 104
+#define GCC_QUPV3_WRAP2_S6_CLK 105
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC 106
+#define GCC_QUPV3_WRAP2_S7_CLK 107
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC 108
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 109
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 110
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 111
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 112
+#define GCC_SDCC1_AHB_CLK 113
+#define GCC_SDCC1_APPS_CLK 114
+#define GCC_SDCC1_APPS_CLK_SRC 115
+#define GCC_SDCC1_ICE_CORE_CLK 116
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 117
+#define GCC_SDCC2_AHB_CLK 118
+#define GCC_SDCC2_APPS_CLK 119
+#define GCC_SDCC2_APPS_CLK_SRC 120
+#define GCC_UFS_PHY_AHB_CLK 121
+#define GCC_UFS_PHY_AXI_CLK 122
+#define GCC_UFS_PHY_AXI_CLK_SRC 123
+#define GCC_UFS_PHY_ICE_CORE_CLK 124
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 125
+#define GCC_UFS_PHY_PHY_AUX_CLK 126
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 127
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 128
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 129
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 130
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 131
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 132
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 133
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135
+#define GCC_USB30_PRIM_ATB_CLK 136
+#define GCC_USB30_PRIM_MASTER_CLK 137
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 138
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141
+#define GCC_USB30_PRIM_SLEEP_CLK 142
+#define GCC_USB3_PRIM_PHY_AUX_CLK 143
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 146
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147
+#define GCC_VIDEO_AHB_CLK 148
+#define GCC_VIDEO_AXI0_CLK 149
+#define GCC_VIDEO_AXI1_CLK 150
+#define GCC_VIDEO_XO_CLK 151
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC 0
+#define GCC_PCIE_0_PHY_GDSC 1
+#define GCC_PCIE_1_GDSC 2
+#define GCC_PCIE_1_PHY_GDSC 3
+#define GCC_UFS_MEM_PHY_GDSC 4
+#define GCC_UFS_PHY_GDSC 5
+#define GCC_USB30_PRIM_GDSC 6
+#define GCC_USB3_PHY_GDSC 7
+
+/* GCC resets */
+#define GCC_CAMERA_BCR 0
+#define GCC_DISPLAY_BCR 1
+#define GCC_GPU_BCR 2
+#define GCC_PCIE_0_BCR 3
+#define GCC_PCIE_0_LINK_DOWN_BCR 4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
+#define GCC_PCIE_0_PHY_BCR 6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
+#define GCC_PCIE_1_BCR 8
+#define GCC_PCIE_1_LINK_DOWN_BCR 9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
+#define GCC_PCIE_1_PHY_BCR 11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
+#define GCC_PCIE_PHY_BCR 13
+#define GCC_PCIE_PHY_CFG_AHB_BCR 14
+#define GCC_PCIE_PHY_COM_BCR 15
+#define GCC_PCIE_RSCC_BCR 16
+#define GCC_PDM_BCR 17
+#define GCC_QUPV3_WRAPPER_1_BCR 18
+#define GCC_QUPV3_WRAPPER_2_BCR 19
+#define GCC_QUSB2PHY_PRIM_BCR 20
+#define GCC_QUSB2PHY_SEC_BCR 21
+#define GCC_SDCC1_BCR 22
+#define GCC_SDCC2_BCR 23
+#define GCC_UFS_PHY_BCR 24
+#define GCC_USB30_PRIM_BCR 25
+#define GCC_USB3_DP_PHY_PRIM_BCR 26
+#define GCC_USB3_DP_PHY_SEC_BCR 27
+#define GCC_USB3_PHY_PRIM_BCR 28
+#define GCC_USB3_PHY_SEC_BCR 29
+#define GCC_USB3PHY_PHY_PRIM_BCR 30
+#define GCC_USB3PHY_PHY_SEC_BCR 31
+#define GCC_VIDEO_AXI0_CLK_ARES 32
+#define GCC_VIDEO_AXI1_CLK_ARES 33
+#define GCC_VIDEO_BCR 34
+#define GCC_CAMERA_HF_AXI_SLP_STG_ARES 37
+#define GCC_CAMERA_SF_AXI_SLP_STG_ARES 38
+#define GCC_CAMERA_HF_AXI_SEL_SLP_STG_ARES 39
+#define GCC_CAMERA_SF_AXI_SEL_SLP_STG_ARES 40
+#define GCC_CAMERA_HF_CLK_EN_SLP_STG 41
+#define GCC_CAMERA_SF_CLK_EN_SLP_STG 42
+#define GCC_CAMERA_HF_CLK_EN_SEL_SLP_STG 43
+#define GCC_CAMERA_SF_CLK_EN_SEL_SLP_STG 44
+
+#endif
--
2.48.1
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