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Message-Id: <20260123-mahua_icc-v1-1-bc82cb087f1e@oss.qualcomm.com>
Date: Fri, 23 Jan 2026 17:12:35 +0000
From: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
To: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Subject: [PATCH 1/2] dt-bindings: interconnect: document the RPMh
Network-On-Chip interconnect in Mahua SoC
Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm
Mahua platform.
Mahua is a derivative of the Glymur SoC. Many interconnect nodes are
identical and continue to use Glymur fallback compatibles. Mahua
introduces SoC-specific configurations and topologies for several
NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs.
This updates the existing Glymur yaml schema to include Mahua-specific
compatible strings, using two-cell "fallback" compatibles wherever
the hardware is identical with Glymur.
Co-developed-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
---
.../bindings/interconnect/qcom,glymur-rpmh.yaml | 132 +++++++++++++++++----
1 file changed, 109 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
index d55a7bcf5591eea79c173a12b12c659321ca3c2e..723ae547ae06073b7fa93dc7a94f33336068519b 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
+title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
maintainers:
- Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
@@ -21,28 +21,98 @@ description: |
properties:
compatible:
- enum:
- - qcom,glymur-aggre1-noc
- - qcom,glymur-aggre2-noc
- - qcom,glymur-aggre3-noc
- - qcom,glymur-aggre4-noc
- - qcom,glymur-clk-virt
- - qcom,glymur-cnoc-cfg
- - qcom,glymur-cnoc-main
- - qcom,glymur-hscnoc
- - qcom,glymur-lpass-ag-noc
- - qcom,glymur-lpass-lpiaon-noc
- - qcom,glymur-lpass-lpicx-noc
- - qcom,glymur-mc-virt
- - qcom,glymur-mmss-noc
- - qcom,glymur-nsinoc
- - qcom,glymur-nsp-noc
- - qcom,glymur-oobm-ss-noc
- - qcom,glymur-pcie-east-anoc
- - qcom,glymur-pcie-east-slv-noc
- - qcom,glymur-pcie-west-anoc
- - qcom,glymur-pcie-west-slv-noc
- - qcom,glymur-system-noc
+ oneOf:
+ - items:
+ - enum:
+ - qcom,mahua-clk-virt
+ - const: qcom,glymur-clk-virt
+ - items:
+ - enum:
+ - qcom,mahua-cnoc-main
+ - const: qcom,glymur-cnoc-main
+ - items:
+ - enum:
+ - qcom,mahua-system-noc
+ - const: qcom,glymur-system-noc
+ - items:
+ - enum:
+ - qcom,mahua-pcie-east-anoc
+ - const: qcom,glymur-pcie-east-anoc
+ - items:
+ - enum:
+ - qcom,mahua-aggre1-noc
+ - const: qcom,glymur-aggre1-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre2-noc
+ - const: qcom,glymur-aggre2-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre3-noc
+ - const: qcom,glymur-aggre3-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre4-noc
+ - const: qcom,glymur-aggre4-noc
+ - items:
+ - enum:
+ - qcom,mahua-mmss-noc
+ - const: qcom,glymur-mmss-noc
+ - items:
+ - enum:
+ - qcom,mahua-pcie-east-slv-noc
+ - const: qcom,glymur-pcie-east-slv-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-lpiaon-noc
+ - const: qcom,glymur-lpass-lpiaon-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-lpicx-noc
+ - const: qcom,glymur-lpass-lpicx-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-ag-noc
+ - const: qcom,glymur-lpass-ag-noc
+ - items:
+ - enum:
+ - qcom,mahua-nsinoc
+ - const: qcom,glymur-nsinoc
+ - items:
+ - enum:
+ - qcom,mahua-oobm-ss-noc
+ - const: qcom,glymur-oobm-ss-noc
+ - items:
+ - enum:
+ - qcom,mahua-nsp-noc
+ - const: qcom,glymur-nsp-noc
+ - enum:
+ - qcom,glymur-aggre1-noc
+ - qcom,glymur-aggre2-noc
+ - qcom,glymur-aggre3-noc
+ - qcom,glymur-aggre4-noc
+ - qcom,glymur-clk-virt
+ - qcom,glymur-cnoc-cfg
+ - qcom,glymur-cnoc-main
+ - qcom,glymur-hscnoc
+ - qcom,glymur-lpass-ag-noc
+ - qcom,glymur-lpass-lpiaon-noc
+ - qcom,glymur-lpass-lpicx-noc
+ - qcom,glymur-mc-virt
+ - qcom,glymur-mmss-noc
+ - qcom,glymur-nsinoc
+ - qcom,glymur-nsp-noc
+ - qcom,glymur-oobm-ss-noc
+ - qcom,glymur-pcie-east-anoc
+ - qcom,glymur-pcie-east-slv-noc
+ - qcom,glymur-pcie-west-anoc
+ - qcom,glymur-pcie-west-slv-noc
+ - qcom,glymur-system-noc
+ - qcom,mahua-mc-virt
+ - qcom,mahua-cnoc-cfg
+ - qcom,mahua-pcie-west-anoc
+ - qcom,mahua-pcie-west-slv-noc
+ - qcom,mahua-hscnoc
reg:
maxItems: 1
@@ -63,6 +133,7 @@ allOf:
enum:
- qcom,glymur-clk-virt
- qcom,glymur-mc-virt
+ - qcom,mahua-mc-virt
then:
properties:
reg: false
@@ -85,6 +156,20 @@ allOf:
- description: aggre PCIE_4 WEST AXI clock
- description: aggre PCIE_6 WEST AXI clock
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,mahua-pcie-west-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre PCIE_3B WEST AXI clock
+ - description: aggre PCIE_4 WEST AXI clock
+ - description: aggre PCIE_6 WEST AXI clock
+
- if:
properties:
compatible:
@@ -132,6 +217,7 @@ allOf:
contains:
enum:
- qcom,glymur-pcie-west-anoc
+ - qcom,mahua-pcie-west-anoc
- qcom,glymur-pcie-east-anoc
- qcom,glymur-aggre2-noc
- qcom,glymur-aggre4-noc
--
2.43.0
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