linux-kernel - Re: [PATCH rc v7 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases

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Message-ID: <176917607019.801728.614554722771260022.b4-ty@kernel.org>
Date: Fri, 23 Jan 2026 17:49:51 +0000
From: Will Deacon <will@...nel.org>
To: Nicolin Chen <nicolinc@...dia.com>
Cc: catalin.marinas@....com,
	kernel-team@...roid.com,
	Will Deacon <will@...nel.org>,
	robin.murphy@....com,
	joro@...tes.org,
	linux-arm-kernel@...ts.infradead.org,
	iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	skolothumtho@...dia.com,
	praan@...gle.com,
	xueshuai@...ux.alibaba.com,
	smostafa@...gle.com,
	Jason Gunthorpe <jgg@...pe.ca>
Subject: Re: [PATCH rc v7 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases

On Thu, 15 Jan 2026 10:23:27 -0800, Nicolin Chen wrote:
> Occasional C_BAD_STE errors were observed in nesting setups where a device
> attached to a nested bypass/identity domain enables PASID.
> 
> This occurred when the physical STE was updated from S2-only mode to S1+S2
> nesting mode, but the update failed to use the hitless routine that it was
> supposed to use. Instead, it cleared STE.V bit to load the CD table, while
> the default substream was still actively performing DMA.
> 
> [...]

Applied to iommu (arm/smmu/updates), thanks!

[1/4] iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence
      https://git.kernel.org/iommu/c/2781f2a930ab
[2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence
      https://git.kernel.org/iommu/c/f3c1d372dbb8
[3/4] iommu/arm-smmu-v3: Mark EATS_TRANS safe when computing the update sequence
      https://git.kernel.org/iommu/c/7cad80048595
[4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage
      https://git.kernel.org/iommu/c/a4f976edcb87

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
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