linux-kernel - Re: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support

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Message-ID: <vpaz7jhnuagfl24dow3ktyhjtzktmhiiwh2rnflub3jbc3pgu2@2ydlmugmqgbt>
Date: Fri, 23 Jan 2026 19:58:13 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Cc: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Subject: Re: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support

On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. This patch extends the

Documentation/process/submitting-patches.rst, look for 'This patch'.

> Glymur driver to support Mahua by:
> 
>   1. Adding new node definitions for interconnects that differ from Glymur
>      (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>   2. Reusing existing Glymur definitions for identical NoCs.
>   3. Overriding the channel and buswidth, with Mahua specific values for
>      the differing NoCs
> 
> Co-developed-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
> ---
>  drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 152 insertions(+), 1 deletion(-)
> 
> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {

As you are patching other instances, why can't we just patch out the
PCI_3A out of these structures?

>  
> +static int glymur_qnoc_probe(struct platform_device *pdev)
> +{
> +	if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
> +		llcc_mc.channels = 8;
> +		ebi.channels = 8;
> +	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
> +		qns_llcc.channels = 8;
> +		chm_apps.channels = 4;
> +		qnm_pcie_west.buswidth = 32;
> +	} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
> +		qns_pcie_west_mem_noc.buswidth = 32;
> +	}

Right here, set the node entries to NULL.

> +
> +	return qcom_icc_rpmh_probe(pdev);
> +}
> +
>  static const struct of_device_id qnoc_of_match[] = {
>  	{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
>  	{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
> @@ -2477,12 +2623,15 @@ static const struct of_device_id qnoc_of_match[] = {
>  	{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
>  	{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
>  	{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
> +	{ .compatible = "qcom,mahua-cnoc-cfg", .data = &mahua_cnoc_cfg},
>  	{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
>  	{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
> +	{ .compatible = "qcom,mahua-hscnoc", .data = &mahua_hscnoc},
>  	{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
>  	{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
>  	{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
>  	{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
> +	{ .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
>  	{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
>  	{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
>  	{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
> @@ -2490,14 +2639,16 @@ static const struct of_device_id qnoc_of_match[] = {
>  	{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
>  	{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
>  	{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
> +	{ .compatible = "qcom,mahua-pcie-west-anoc", .data = &mahua_pcie_west_anoc},
>  	{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
> +	{ .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &mahua_pcie_west_slv_noc},
>  	{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, qnoc_of_match);
>  
>  static struct platform_driver qnoc_driver = {
> -	.probe = qcom_icc_rpmh_probe,
> +	.probe = glymur_qnoc_probe,
>  	.remove = qcom_icc_rpmh_remove,
>  	.driver = {
>  		.name = "qnoc-glymur",
> 
> -- 
> 2.43.0
> 

-- 
With best wishes
Dmitry