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Message-ID: <665f3d43-7f0b-4efc-9092-2a1f7234ddaf@nvidia.com>
Date: Fri, 23 Jan 2026 15:48:04 -0800
From: John Hubbard <jhubbard@...dia.com>
To: Gary Guo <gary@...yguo.net>, Danilo Krummrich <dakr@...nel.org>
Cc: Alexandre Courbot <acourbot@...dia.com>,
Joel Fernandes <joelagnelf@...dia.com>, Timur Tabi <ttabi@...dia.com>,
Alistair Popple <apopple@...dia.com>, Edwin Peer <epeer@...dia.com>,
Zhi Wang <zhiw@...dia.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Bjorn Helgaas <bhelgaas@...gle.com>,
Miguel Ojeda <ojeda@...nel.org>, Alex Gaynor <alex.gaynor@...il.com>,
Boqun Feng <boqun.feng@...il.com>, Björn Roy Baron
<bjorn3_gh@...tonmail.com>, Benno Lossin <lossin@...nel.org>,
Andreas Hindborg <a.hindborg@...nel.org>, Alice Ryhl <aliceryhl@...gle.com>,
Trevor Gross <tmgross@...ch.edu>, nouveau@...ts.freedesktop.org,
rust-for-linux@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 15/31] gpu: nova-core: Hopper/Blackwell: add FSP falcon
EMEM operations
On 1/21/26 8:06 AM, Gary Guo wrote:
> On Wed Dec 3, 2025 at 5:59 AM GMT, John Hubbard wrote:
>> Add external memory (EMEM) read/write operations to the GPU's FSP falcon
>> engine. These operations use Falcon PIO (Programmed I/O) to communicate
>> with the FSP through indirect memory access.
>>
>> Signed-off-by: John Hubbard <jhubbard@...dia.com>
>> ---
>> drivers/gpu/nova-core/falcon/fsp.rs | 60 ++++++++++++++++++++++++++++-
>> drivers/gpu/nova-core/regs.rs | 10 +++++
>> 2 files changed, 69 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs
>> index 7323ae2f2302..9e796e82e556 100644
>> --- a/drivers/gpu/nova-core/falcon/fsp.rs
>> +++ b/drivers/gpu/nova-core/falcon/fsp.rs
>> @@ -5,15 +5,27 @@
>> //! The FSP falcon handles secure boot and Chain of Trust operations
>> //! on Hopper and Blackwell architectures, replacing SEC2's role.
>>
>> +use kernel::prelude::*;
>> +
>> use crate::{
>> + driver::Bar0,
>> falcon::{
>> + Falcon,
>> FalconEngine,
>> PFalcon2Base,
>> PFalconBase, //
>> },
>> - regs::macros::RegisterBase,
>> + regs::{
>> + self,
>> + macros::RegisterBase, //
>> + },
>> };
>>
>> +/// EMEM control register bit 24: write mode.
>> +const EMEM_CTL_WRITE: u32 = 1 << 24;
>> +/// EMEM control register bit 25: read mode.
>> +const EMEM_CTL_READ: u32 = 1 << 25;
>> +
>> /// Type specifying the `Fsp` falcon engine. Cannot be instantiated.
>> #[allow(dead_code)]
>> pub(crate) struct Fsp(());
>> @@ -30,3 +42,49 @@ impl RegisterBase<PFalcon2Base> for Fsp {
>> impl FalconEngine for Fsp {
>> const ID: Self = Fsp(());
>> }
>> +
>> +impl Falcon<Fsp> {
>> + /// Writes `data` to FSP external memory at byte `offset` using Falcon PIO.
>> + ///
>> + /// Returns `EINVAL` if offset or data length is not 4-byte aligned.
>> + #[allow(dead_code)]
>> + pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) -> Result {
>> + if offset % 4 != 0 || data.len() % 4 != 0 {
>
> I was about to suggest `is_multiple_of`, but then realize that it's only
> available in Rust 1.82+...
OK, I've added TODO's for that.
>
>> + return Err(EINVAL);
>> + }
>> +
>> + regs::NV_PFALCON_FALCON_EMEM_CTL::default()
>> + .set_value(EMEM_CTL_WRITE | offset)
>> + .write(bar, &Fsp::ID);
>> +
>> + for chunk in data.chunks_exact(4) {
>> + let word = u32::from_le_bytes([chunk[0], chunk[1], chunk[2], chunk[3]]);
>
> Use `as_chunks()` can save you from doing this.
>
> Also, a typical pattern is `chunk.try_into().unwrap()` -- yes it has an unwrap
> as `[T]` -> `[T; N]` can fail in general, but not with `chunks_exact`.
>
Here, I recall having a discussion or two about it, and we concluded
that we'd rather avoid having to justify an "infallible .unwrap()",
in favor of just writing out the four chunks. I still like that in this
particular case, it's just one less "// PANIC: " to *not* have to deal
with. In other words, one line of code, instead of a line plus one or
two lines of special comments that someone will later try to turn into
a proof. haha :)
thanks,
--
John Hubbard
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