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Message-Id: <20260123-enable-etr-and-ctcu-devices-v1-1-5fbb3423a2d7@oss.qualcomm.com>
Date: Fri, 23 Jan 2026 15:10:46 +0800
From: Jie Gan <jie.gan@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Tingwei Zhang <tingwei.zhang@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Jie Gan <jie.gan@....qualcomm.com>
Subject: [PATCH] arm64: dts: qcom: talos: add ETR device
Add the TMC ETR device to store collected trace data in DDR memory.
Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 75716b4a58d6..3b081ce9d202 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -2253,6 +2253,14 @@ out-ports {
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ replicator0_out0: endpoint {
+ remote-endpoint = <&tmc_etr_in>;
+ };
+ };
+
port@1 {
reg = <1>;
@@ -2287,6 +2295,25 @@ tmc_etf_out: endpoint {
};
};
+ tmc_etr: tmc@...8000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x06048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ iommus = <&apps_smmu 0x01e0 0x0>;
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ tmc_etr_in: endpoint {
+ remote-endpoint = <&replicator0_out0>;
+ };
+ };
+ };
+ };
+
replicator@...a000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x0604a000 0x0 0x1000>;
---
base-commit: a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d
change-id: 20260123-enable-etr-and-ctcu-devices-0b1386899261
Best regards,
--
Jie Gan <jie.gan@....qualcomm.com>
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