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Message-Id: <20260123-qcom_ice_power_and_clk_vote-v1-1-e9059776f85c@qti.qualcomm.com>
Date: Fri, 23 Jan 2026 12:41:25 +0530
From: Harshal Dev <harshal.dev@....qualcomm.com>
To: Herbert Xu <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Abel Vesa <abel.vesa@....qualcomm.com>,
cros-qcom-dts-watchers@...omium.org
Cc: Brian Masney <bmasney@...hat.com>,
Neeraj Soni <neeraj.soni@....qualcomm.com>,
Gaurav Kashyap <gaurav.kashyap@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-crypto@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Harshal Dev <harshal.dev@....qualcomm.com>
Subject: [PATCH 01/11] dt-bindings: crypto: qcom,ice: Require power-domain
and iface clk
Update the inline-crypto engine DT binding to reflect that power-domain and
clock-names are now mandatory. Also update the maximum number of clocks
that can be specified to two. These new fields are mandatory because ICE
needs to vote on the power domain before it attempts to vote on the core
and iface clocks to avoid clock 'stuck' issues.
Signed-off-by: Harshal Dev <harshal.dev@....qualcomm.com>
---
.../bindings/crypto/qcom,inline-crypto-engine.yaml | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index c3408dcf5d20..1c2416117d4c 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -28,12 +28,20 @@ properties:
maxItems: 1
clocks:
+ maxItems: 2
+
+ clock-names:
+ maxItems: 2
+
+ power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
+ - clock-names
+ - power-domains
additionalProperties: false
@@ -45,6 +53,10 @@ examples:
compatible = "qcom,sm8550-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x01d88000 0x8000>;
- clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>;
+ clock-names = "ice_core_clk",
+ "iface_clk";
+ power-domains = <&gcc UFS_PHY_GDSC>;
};
...
--
2.34.1
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