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Message-ID: <20260123-upstream_uboot_properties-v5-6-5167929d5af5@foss.st.com>
Date: Fri, 23 Jan 2026 11:14:08 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Maxime Coquelin
<mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>, Christoph Niedermaier
<cniedermaier@...electronics.com>, Marek Vasut <marex@...x.de>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<kernel@...electronics.com>, Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH v5 6/6] arm64: dts: st: Add boot phase tags for
STMicroelectronics mp2 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 25 +++++++
arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +-
arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +-
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++++++++++++++++++
8 files changed, 335 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index bf888d60cd4f..9e9f7f6a580f 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -47,7 +47,7 @@ ck_flexgen_51: clock-200000000 {
};
firmware {
- optee {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
@@ -70,7 +70,7 @@ scmi_reset: protocol@16 {
};
};
- psci {
+ psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
index 7bdaeaa5ab0f..2a003a7c3796 100644
--- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
@@ -44,6 +44,31 @@ &arm_wdt {
status = "okay";
};
+&optee {
+ bootph-all;
+};
+
+&psci {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
+&scmi_reset {
+ bootph-all;
+};
+
&usart2 {
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 88e214d395ab..a2f93f6ccb84 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -59,7 +59,7 @@ optee: optee {
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
- scmi {
+ scmi: scmi {
compatible = "linaro,scmi-optee";
#address-cells = <1>;
#size-cells = <0>;
@@ -111,7 +111,7 @@ scmi_vdda18adc: regulator@7 {
};
};
- psci {
+ psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
index c3e688068223..a055d8a2ee99 100644
--- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
@@ -78,6 +78,10 @@ &arm_wdt {
status = "okay";
};
+&bsec {
+ bootph-all;
+};
+
ðernet1 {
pinctrl-0 = <ð1_rgmii_pins_b>;
pinctrl-1 = <ð1_rgmii_sleep_pins_b>;
@@ -100,6 +104,78 @@ phy1_eth1: ethernet-phy@1 {
};
};
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
+&optee {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&pinctrl_z {
+ bootph-all;
+};
+
+&psci {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
@@ -111,6 +187,10 @@ scmi_vdd_sdcard: regulator@23 {
};
};
+&scmi_reset {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -125,12 +205,27 @@ &sdmmc1 {
status = "okay";
};
+&syscfg {
+ bootph-all;
+};
+
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index a8e6e0f77b83..4eaf1de3d87f 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -68,7 +68,7 @@ optee: optee {
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
- scmi {
+ scmi: scmi {
compatible = "linaro,scmi-optee";
#address-cells = <1>;
#size-cells = <0>;
@@ -139,7 +139,7 @@ v2m0: v2m@...90000 {
};
};
- psci {
+ psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..3ba4e6166586 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -40,4 +40,4 @@ venc: venc@...e0000 {
clocks = <&rcc CK_BUS_VENC>;
access-controllers = <&rifsc 90>;
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
index e718d888ce21..080358b134ce 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
@@ -78,6 +78,10 @@ &arm_wdt {
status = "okay";
};
+&bsec {
+ bootph-all;
+};
+
ðernet1 {
pinctrl-0 = <ð1_rgmii_pins_b>;
pinctrl-1 = <ð1_rgmii_sleep_pins_b>;
@@ -100,6 +104,86 @@ phy1_eth1: ethernet-phy@1 {
};
};
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
+&optee {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&pinctrl_z {
+ bootph-all;
+};
+
+&psci {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
@@ -111,6 +195,10 @@ scmi_vdd_sdcard: regulator@23 {
};
};
+&scmi_reset {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -125,12 +213,27 @@ &sdmmc1 {
status = "okay";
};
+&syscfg {
+ bootph-all;
+};
+
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 6e165073f732..61464076b8d5 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -130,6 +130,10 @@ &arm_wdt {
status = "okay";
};
+&bsec {
+ bootph-all;
+};
+
&combophy {
clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>;
clock-names = "apb", "ker", "pad";
@@ -216,6 +220,54 @@ phy0_eth2: ethernet-phy@1 {
};
};
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
@@ -300,6 +352,7 @@ timer {
};
<dc {
+ bootph-all;
status = "okay";
port {
ltdc_ep0_out: endpoint {
@@ -309,6 +362,7 @@ ltdc_ep0_out: endpoint {
};
&lvds {
+ bootph-all;
status = "okay";
ports {
#address-cells = <1>;
@@ -330,6 +384,10 @@ lvds_out0: endpoint {
};
};
+&optee {
+ bootph-all;
+};
+
&pcie_ep {
pinctrl-names = "default", "init";
pinctrl-0 = <&pcie_pins_a>;
@@ -351,10 +409,38 @@ pcie@0,0 {
};
};
+&pinctrl {
+ bootph-all;
+};
+
+&pinctrl_z {
+ bootph-all;
+};
+
+&psci {
+ bootph-all;
+};
+
+&rcc {
+ bootph-all;
+};
+
&rtc {
status = "okay";
};
+&rifsc {
+ bootph-all;
+};
+
+&scmi {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
@@ -386,6 +472,10 @@ scmi_vdd_sdcard: regulator@23 {
};
};
+&scmi_reset {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -400,6 +490,10 @@ &sdmmc1 {
status = "okay";
};
+&syscfg {
+ bootph-all;
+};
+
&spi3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_pins_a>;
@@ -477,11 +571,22 @@ &usart2 {
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_idle_pins_a>;
pinctrl-2 = <&usart2_sleep_pins_a>;
+ bootph-all;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usart6 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart6_pins_a>;
--
2.43.0
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