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Message-ID: <bc107957-dd07-4e12-8c54-57b2f40e9d94@nvidia.com>
Date: Sun, 25 Jan 2026 02:22:04 +0530
From: Sumit Gupta <sumitg@...dia.com>
To: "zhenglifeng (A)" <zhenglifeng1@...wei.com>
Cc: rafael@...nel.org, viresh.kumar@...aro.org, pierre.gondois@....com,
ionela.voinescu@....com, lenb@...nel.org, robert.moore@...el.com,
corbet@....net, rdunlap@...radead.org, ray.huang@....com,
gautham.shenoy@....com, mario.limonciello@....com, perry.yuan@....com,
zhanjie9@...ilicon.com, linux-pm@...r.kernel.org,
linux-acpi@...r.kernel.org, linux-doc@...r.kernel.org,
acpica-devel@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org, treding@...dia.com, jonathanh@...dia.com,
vsethi@...dia.com, ksitaraman@...dia.com, sanjayc@...dia.com,
nhartman@...dia.com, bbasu@...dia.com, sumitg@...dia.com
Subject: Re: [PATCH v6 6/9] ACPI: CPPC: add APIs and sysfs interface for
min/max_perf
On 22/01/26 18:05, zhenglifeng (A) wrote:
> External email: Use caution opening links or attachments
>
>
> On 2026/1/20 22:56, Sumit Gupta wrote:
>> Add cppc_get/set_min_perf() and cppc_get/set_max_perf() APIs to read and
>> write the MIN_PERF and MAX_PERF registers.
>>
>> Also add sysfs interfaces (min_perf, max_perf) in cppc_cpufreq driver
>> to expose these controls to userspace. The sysfs values are in frequency
>> (kHz) for consistency with other cpufreq sysfs files.
>>
>> A mutex is used to serialize sysfs store operations to ensure hardware
>> register writes and perf_ctrls updates are atomic.
>>
>> Signed-off-by: Sumit Gupta <sumitg@...dia.com>
>> ---
>> drivers/acpi/cppc_acpi.c | 44 +++++++++
>> drivers/cpufreq/cppc_cpufreq.c | 157 +++++++++++++++++++++++++++++++++
>> include/acpi/cppc_acpi.h | 20 +++++
>> 3 files changed, 221 insertions(+)
>>
>> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
>> index 45c6bd6ec24b..46bf45f8b0f3 100644
>> --- a/drivers/acpi/cppc_acpi.c
>> +++ b/drivers/acpi/cppc_acpi.c
>> @@ -1743,6 +1743,50 @@ int cppc_set_auto_sel(int cpu, bool enable)
>> }
>> EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
>>
>> +/**
>> + * cppc_get_min_perf - Read minimum performance register.
>> + * @cpu: CPU from which to read register.
>> + * @min_perf: Return address.
>> + */
>> +int cppc_get_min_perf(int cpu, u64 *min_perf)
>> +{
>> + return cppc_get_reg_val(cpu, MIN_PERF, min_perf);
>> +}
>> +EXPORT_SYMBOL_GPL(cppc_get_min_perf);
>> +
>> +/**
>> + * cppc_set_min_perf - Write minimum performance register.
>> + * @cpu: CPU to which to write register.
>> + * @min_perf: the desired minimum performance value to be updated.
>> + */
>> +int cppc_set_min_perf(int cpu, u32 min_perf)
>> +{
>> + return cppc_set_reg_val(cpu, MIN_PERF, min_perf);
> ACPI spec says it 'must be set to a value that is less than or equal to
> that specified by the Maximum Performance Register'. So it may be better
> to check it before setting value.
Yes, I added that check in v1[1]. But missed adding it in later versions.
Will add below check in v7. Thank you for pointing.
--------
static ssize_t store_min_perf(struct cpufreq_policy *policy, const
char *buf,
size_t count)
{
.....
/* Convert frequency (kHz) to performance value */
perf = cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz);
+ if (perf > cpu_data->perf_ctrls.max_perf)
+ return -EINVAL;
--------
[1] https://lore.kernel.org/lkml/20250211103737.447704-4-sumitg@nvidia.com/
>> +}
>> +EXPORT_SYMBOL_GPL(cppc_set_min_perf);
>> +
>> +/**
>> + * cppc_get_max_perf - Read maximum performance register.
>> + * @cpu: CPU from which to read register.
>> + * @max_perf: Return address.
>> + */
>> +int cppc_get_max_perf(int cpu, u64 *max_perf)
>> +{
>> + return cppc_get_reg_val(cpu, MAX_PERF, max_perf);
>> +}
>> +EXPORT_SYMBOL_GPL(cppc_get_max_perf);
>> +
>> +/**
>> + * cppc_set_max_perf - Write maximum performance register.
>> + * @cpu: CPU to which to write register.
>> + * @max_perf: the desired maximum performance value to be updated.
>> + */
>> +int cppc_set_max_perf(int cpu, u32 max_perf)
>> +{
>> + return cppc_set_reg_val(cpu, MAX_PERF, max_perf);
>> +}
>> +EXPORT_SYMBOL_GPL(cppc_set_max_perf);
>> +
>> /**
>> * cppc_set_enable - Set to enable CPPC on the processor by writing the
>> * Continuous Performance Control package EnableRegister field.
>> diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
>> index 229880c4eedb..66e183b45fb0 100644
>> --- a/drivers/cpufreq/cppc_cpufreq.c
>> +++ b/drivers/cpufreq/cppc_cpufreq.c
>> @@ -28,6 +28,8 @@
>>
>> static struct cpufreq_driver cppc_cpufreq_driver;
>>
>> +static DEFINE_MUTEX(cppc_cpufreq_autonomous_lock);
>> +
>> #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE
>> static enum {
>> FIE_UNSET = -1,
>> @@ -570,6 +572,35 @@ static void populate_efficiency_class(void)
>> }
>> #endif
>>
>> +/* Set min/max performance HW register and cache the value */
>> +static int cppc_cpufreq_set_mperf_reg(struct cpufreq_policy *policy,
>> + u64 val, bool is_min)
>> +{
>> + struct cppc_cpudata *cpu_data = policy->driver_data;
>> + struct cppc_perf_caps *caps = &cpu_data->perf_caps;
>> + unsigned int cpu = policy->cpu;
>> + u32 perf;
>> + int ret;
>> +
>> + perf = clamp(val, caps->lowest_perf, caps->highest_perf);
>> +
>> + ret = is_min ? cppc_set_min_perf(cpu, perf) :
>> + cppc_set_max_perf(cpu, perf);
>> + if (ret) {
>> + if (ret != -EOPNOTSUPP)
>> + pr_warn("CPU%d: set %s_perf=%u failed (%d)\n",
>> + cpu, is_min ? "min" : "max", perf, ret);
>> + return ret;
>> + }
>> +
>> + if (is_min)
>> + cpu_data->perf_ctrls.min_perf = perf;
>> + else
>> + cpu_data->perf_ctrls.max_perf = perf;
>> +
>> + return 0;
> I think cppc_set_XXX and updating cpudata->perf_ctrls.XXX can be extract
> out for not only min_perf and max_perf but also auto_sel and energy_perf
> and anything else in perf_ctrls.
Updating cached value of auto_sel and energy_perf in patch 9.
I think the current code is simple. Adding an abstraction seems to be
overdoing it for this case.
Thank you,
Sumit Gupta
....
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