linux-kernel - Re: [PATCH RFT 2/3] arm64: dts: qcom: glymur: Add USB related nodes

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Message-ID: <wh4qsgwl6drye2d227mv22pxz57cikp6ogabklo6fvlzljqafp@sgps7d52yp2d>
Date: Mon, 26 Jan 2026 16:31:44 +0200
From: Abel Vesa <abel.vesa@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Wesley Cheng <quic_wcheng@...cinc.com>,
        Pankaj Patil <pankaj.patil@....qualcomm.com>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
        Wesley Cheng <wesley.cheng@....qualcomm.com>
Subject: Re: [PATCH RFT 2/3] arm64: dts: qcom: glymur: Add USB related nodes

On 26-01-13 14:13:32, Konrad Dybcio wrote:
> On 1/13/26 1:33 PM, Abel Vesa wrote:
> > From: Wesley Cheng <wesley.cheng@....qualcomm.com>
> > 
> > The Glymur USB system contains 3 USB type C ports, 1 USB multiport
> > controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
> > PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
> > DWC3 based, so describe them as flattened DWC3 QCOM nodes.
> > 
> > Signed-off-by: Wesley Cheng <wesley.cheng@....qualcomm.com>
> > Co-developed-by: Abel Vesa <abel.vesa@....qualcomm.com>
> > Signed-off-by: Abel Vesa <abel.vesa@....qualcomm.com>
> > ---
> 
> [...]
> 
> >  
> > +		usb_mp_hsphy0: phy@...000 {
> > +			compatible = "qcom,glymur-m31-eusb2-phy",
> > +				     "qcom,sm8750-m31-eusb2-phy";
> > +
> > +			reg = <0 0x00fa1000 0 0x29c>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> > +			clock-names = "ref";
> > +
> > +			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		usb_mp_hsphy1: phy@...000  {
> > +			compatible = "qcom,glymur-m31-eusb2-phy",
> > +				     "qcom,sm8750-m31-eusb2-phy";
> > +
> > +			reg = <0 0x00fa2000 0 0x29c>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
> > +			clock-names = "ref";
> > +
> > +			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
> > +
> > +			status = "disabled";
> > +		};
> 
> 
> [...]
> 
> > +		usb1_ss0_hsphy: phy@...000 {
> 
> Let's not repeat the mess introduced in hamoa..
> 
> Perhaps let's fall back to usb_0 etc.?

Sure. So then:

USB SS[0-2]              -> usb_[0-2]
USB MP                   -> usb_mp
USB 2.0 (USB20S in docs) -> ?

> 
> [...]
> 
> 
> > +			snps,dis_u2_susphy_quirk;
> > +			snps,dis_enblslpm_quirk;
> > +			snps,dis_u3_susphy_quirk;
> > +			snps,usb2-lpm-disable;
> 
> Other SoCs have a list that's much longer, please consult Wesley if
> this list is enough

Will do.