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Message-ID: <2026012608-slicing-vehicular-6987@gregkh>
Date: Mon, 26 Jan 2026 16:22:48 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Jiri Slaby <jirislaby@...nel.org>, linux-serial@...r.kernel.org,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
qianfan Zhao <qianfanguijin@....com>,
Adriana Nicolae <adriana@...sta.com>,
Markus Mayer <markus.mayer@...aro.org>,
Tim Kryger <tim.kryger@...aro.org>,
Matt Porter <matt.porter@...aro.org>,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Jamie Iles <jamie@...ieiles.com>, linux-kernel@...r.kernel.org,
stable@...r.kernel.org,
"Bandal, Shankar" <shankar.bandal@...el.com>,
"Murthy, Shanth" <shanth.murthy@...el.com>
Subject: Re: [PATCH 6/6] serial: 8250_dw: Ensure BUSY is deasserted
On Fri, Jan 23, 2026 at 07:27:39PM +0200, Ilpo Järvinen wrote:
> DW UART cannot write to LCR, DLL, and DLH while BUSY is asserted.
> Existance of BUSY depends on uart_16550_compatible, if UART HW is
> configured with 16550 compatible those registers can always be written.
>
> There currently is dw8250_force_idle() which attempts to archive
> non-BUSY state by disabling FIFO, however, the solution is unreliable
> when Rx keeps getting more and more characters.
>
> Create a sequence of operations to enforce that ensures UART cannot
> keep BUSY asserted indefinitely. The new sequence relies on enabling
> loopback mode temporarily to prevent incoming Rx characters keeping
> UART BUSY.
>
> Ensure no Tx in ongoing while the UART is switches into the loopback
> mode (requires exporting serial8250_fifo_wait_for_lsr_thre() and adding
> DMA Tx pause/resume functions).
>
> According to tests performed by Adriana Nicolae <adriana@...sta.com>,
> simply disabling FIFO or clearing FIFOs only once does not always
> ensure BUSY is deasserted but up to two tries may be needed. This could
> be related to ongoing Rx of a character (a guess, not known for sure).
> Therefore, retry FIFO clearing a few times (retry limit 4 is arbitrary
> number but using, e.g., p->fifosize seems overly large). Tests
> performed by others did not exhibit similar challenge but it does not
> seem harmful to leave the FIFO clearing loop in place for all DW UARTs
> with BUSY functionality.
>
> Use the new dw8250_idle_enter/exit() to do divisor writes and LCR
> writes. In case of plain LCR writes, opportunistically try to update
> LCR first and only invoke dw8250_idle_enter() if the write did not
> succeed (it has been observed that in practice most LCR writes do
> succeed without complications).
>
> This issue was first reported by qianfan Zhao who put lots of debugging
> effort into understanding the solution space.
>
> Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround")
> Fixes: 7d4008ebb1c9 ("tty: add a DesignWare 8250 driver")
> Cc: <stable@...r.kernel.org>
Why is patch 6/6 only marked for stable? If this is needed "now",
shouldn't this be a separate patch? Do you need all of the first 5 for
this to work properly?
I can't take this series as-is because I don't know how to route it :(
thanks,
greg k-h
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