linux-kernel - Re: [PATCH v2 3/5] clk: versaclock3: Add freerunning 32.768kHz clock support

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Message-ID: <CAMuHMdVB490OOVY6B2Y6DORnWoc0LYvafLKAoRSOqFFP_nybOg@mail.gmail.com>
Date: Mon, 26 Jan 2026 17:12:24 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Ovidiu Panait <ovidiu.panait.rb@...esas.com>
Cc: magnus.damm@...il.com, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org, 
	biju.das.jz@...renesas.com, fabrizio.castro.jz@...esas.com, 
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 3/5] clk: versaclock3: Add freerunning 32.768kHz clock support

Hi Ovidiu,

On Tue, 20 Jan 2026 at 16:06, Ovidiu Panait
<ovidiu.panait.rb@...esas.com> wrote:
> The Versa 3 clock generator has an internal 32.768kHz oscillator that can
> be routed to the SE1, SE2 and SE3 outputs. This patch exposes it as a
> fixed-rate clock ("vc3-clk-32k") and makes it available as a parent for
> the SE1/SE2/SE3 muxes.
>
> The 32.768kHz clock is only intended to be used when explicitly requested
> (i.e. when a rate of exactly 32768Hz is set). Selecting it as a fallback
> for other rates can cause issues, for example in audio configurations.
>
> To enforce this, introduce a new helper function,
> _vc3_clk_mux_determine_rate() which rejects configurations where the
> 32.768kHz parent would otherwise be chosen implicitly.
>
> Two new fields are added to struct vc3_clk_data:
>   - clk_32k_bitmsk: bit mask for selecting the 32.768kHz oscillator
>   - clk_32k_index: index of the 32.768kHz clock in the mux parent list
>
> They are used by clk_mux callbacks to select the appropriate parent clock.
>
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@...esas.com>

Thanks for your patch!

> --- a/drivers/clk/clk-versaclock3.c
> +++ b/drivers/clk/clk-versaclock3.c

> @@ -1038,6 +1087,14 @@ static int vc3_probe(struct i2c_client *client)
>                 return ret;
>         }
>
> +       /* Register fixed 32.768kHz clock */
> +       clk_32k = devm_clk_hw_register_fixed_rate(dev, VC3_CLK_32K_NAME, NULL,
> +                                                 0, VC3_CLK_32K_FREQ);

If you have a system with multiple versaclock3 instances, I believe
this will fail for all but the first instance, as clock names must
be globally unique.  Upon closer look, this is the case for all
other clock names in this driver.  See e.g. commit f491276a51685987
("clk: vc5: Allow Versaclock driver to support multiple instances")
(and subsequent fixes) for how to solve this.

> +       if (IS_ERR(clk_32k))
> +               return dev_err_probe(dev, PTR_ERR(clk_32k),
> +                                    "Failed to register %dHz fixed clock\n",
> +                                    VC3_CLK_32K_FREQ);
> +
>         /* Register pfd muxes */
>         for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) {
>                 clk_pfd_mux[i].regmap = regmap;

 Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds