linux-kernel - Re: [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU

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Message-ID: <cd175b3d-d8d1-4efd-9698-80a6c238d819@arm.com>
Date: Mon, 26 Jan 2026 17:22:29 +0000
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Jie Gan <jie.gan@....qualcomm.com>, Mike Leach <mike.leach@...aro.org>,
 James Clark <james.clark@...aro.org>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Tingwei Zhang <tingwei.zhang@....qualcomm.com>,
 Mao Jinlong <jinlong.mao@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, Krzysztof Kozlowski <krzk@...nel.org>
Subject: Re: [PATCH v10 5/8] dt-bindings: arm: add an interrupt property for
 Coresight CTCU

On 22/01/2026 02:08, Jie Gan wrote:
> Add an interrupt property to CTCU device. The interrupt will be triggered
> when the data size in the ETR buffer exceeds the threshold of the
> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
> of CTCU device will enable the interrupt.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Reviewed-by: Mike Leach <mike.leach@...aro.org>
> Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
> ---
>   Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..ac27a8b89085 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -39,6 +39,11 @@ properties:
>       items:
>         - const: apb
>   
> +  interrupts:
> +    items:
> +      - description: Interrupt for the ETR device connected to in-port0.
> +      - description: Interrupt for the ETR device connected to in-port1.

Is this all the hardware supports ? i.e., can it only have two ports 
ever ? If not, why restrict it to two ?

Suzuki


> +
>     label:
>       description:
>         Description of a coresight device.
> @@ -60,6 +65,8 @@ additionalProperties: false
>   
>   examples:
>     - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
>       ctcu@...1000 {
>           compatible = "qcom,sa8775p-ctcu";
>           reg = <0x1001000 0x1000>;
> @@ -67,6 +74,9 @@ examples:
>           clocks = <&aoss_qmp>;
>           clock-names = "apb";
>   
> +        interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
> +
>           in-ports {
>               #address-cells = <1>;
>               #size-cells = <0>;
>