linux-kernel - [RFC 0/2] Rust PCI capability infrastructure and SR-IOV support

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Message-ID: <20260126215957.541180-1-zhiw@nvidia.com>
Date: Mon, 26 Jan 2026 23:59:55 +0200
From: Zhi Wang <zhiw@...dia.com>
To: <rust-for-linux@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
CC: <dakr@...nel.org>, <aliceryhl@...gle.com>, <bhelgaas@...gle.com>,
	<kwilczynski@...nel.org>, <ojeda@...nel.org>, <alex.gaynor@...il.com>,
	<boqun.feng@...il.com>, <gary@...yguo.net>, <bjorn3_gh@...tonmail.com>,
	<lossin@...nel.org>, <a.hindborg@...nel.org>, <tmgross@...ch.edu>,
	<markus.probst@...teo.de>, <helgaas@...nel.org>, <cjia@...dia.com>,
	<smitra@...dia.com>, <ankita@...dia.com>, <aniketa@...dia.com>,
	<kwankhede@...dia.com>, <targupta@...dia.com>, <acourbot@...dia.com>,
	<joelagnelf@...dia.com>, <jhubbard@...dia.com>, <zhiwang@...nel.org>,
	<daniel.almeida@...labora.com>, Zhi Wang <zhiw@...dia.com>
Subject: [RFC 0/2] Rust PCI capability infrastructure and SR-IOV support

This RFC series introduces PCI capability discovery and access
infrastructure for Rust kernel drivers, with initial support for SR-IOV
(Single Root I/O Virtualization) capabilities.

Background
----------
Modern PCI devices expose advanced features through capability structures
in configuration space. Rust drivers need type-safe, ergonomic APIs to
discover and access these capabilities while maintaining the kernel's
existing safety guarantees. An example can be found in RFC patch. [1]

Overview
--------
Patch 1 extends ConfigSpace with fallible I/O methods that properly handle
PCI bus errors, providing the foundation for safe capability access with
runtime-determined offsets.

Patch 2 introduces the core capability infrastructure:
- Generic Capability<S, K> struct with Io trait implementation
- Capability size calculation using kernel's capability chaining
- SriovCapability wrapper for accessing VF configuration registers
- Support for reading VF Offset and VF BAR0/1/2 registers

Feedback Requested
------------------

1) The configuration cap doesn't have an fixed offset, thus it doesn't fit
with the infallible accessors. But to have fallible accessors, it needs the
config space backend to implement the fallible accessors as well. I tried
different approaches, this seems the most reasonable one. Any thought?

2) Capability traits hierarchy

I was thinking several solutions of arranging common functions for
Normal/Extended caps, all the extended caps. It seems a complicated traits
hierarchy again. Would like to hear more about this.

[1] https://lore.kernel.org/all/20251206124208.305963-5-zhiw@nvidia.com/

Zhi Wang (2):
  pci: Add fallible I/O methods to ConfigSpace
  pci: Add PCI capability infrastructure and SR-IOV capability support

 rust/kernel/pci.rs     |   9 ++
 rust/kernel/pci/cap.rs | 274 +++++++++++++++++++++++++++++++++++++++++
 rust/kernel/pci/io.rs  |  34 ++++-
 3 files changed, 314 insertions(+), 3 deletions(-)
 create mode 100644 rust/kernel/pci/cap.rs

-- 
2.51.0