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Message-ID: <20260126074519.3426742-7-mmaddireddy@nvidia.com>
Date: Mon, 26 Jan 2026 13:15:03 +0530
From: Manikanta Maddireddy <mmaddireddy@...dia.com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kwilczynski@...nel.org>,
<mani@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<jingoohan1@...il.com>, <vidyas@...dia.com>, <cassel@...nel.org>,
<18255117159@....com>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>, "Manikanta
Maddireddy" <mmaddireddy@...dia.com>
Subject: [PATCH V4 06/22] PCI: tegra194: Disable direct speed change for EP
From: Vidya Sagar <vidyas@...dia.com>
Disable direct speed change for the endpoint to prevent it from initiating
the speed change post physical layer link up at gen1. This leaves the speed
change ownership with the host.
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@...dia.com>
---
V4:
* None
V3:
* Reworded the commit message
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index d3d577d5f67b..25f933a578ae 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1841,6 +1841,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
reset_control_deassert(pcie->core_rst);
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
--
2.34.1
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