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Message-ID: <90c9fac9-3c55-492e-a0af-3d379164727e@oss.qualcomm.com>
Date: Mon, 26 Jan 2026 11:55:15 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Taniya Das <taniya.das@....qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@....qualcomm.com>
Cc: Vikash Garodia <vikash.garodia@....qualcomm.com>,
Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
Bryan O'Donoghue <bod@...nel.org>,
Mauro Carvalho Chehab
<mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Bjorn Andersson <andersson@...nel.org>,
David Heidelberg <david@...t.cz>, linux-media@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Johan Hovold <johan+linaro@...nel.org>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v3 4/7] arm64: dts: qcom: sc8280xp: Add Venus
On 1/26/26 11:47 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 26, 2026 at 11:00:25AM +0100, Konrad Dybcio wrote:
>> On 1/25/26 4:33 PM, Dmitry Baryshkov wrote:
>>> From: Konrad Dybcio <konradybcio@...nel.org>
>>>
>>> Add the required nodes to enable Venus on sc8280xp.
>>>
>>> [ bod: added interconnect tags ]
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
>>> [ johan: use sm8350 videocc defines ]
>>> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
>>> [ bod: dropped video encoder/decoder declarations ]
>>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
>>> [ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + venus_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-720000000 {
>>> + opp-hz = /bits/ 64 <720000000>;
>>
>> You need to div3 all of these, otherwise this LOW_SVS OPP
>> will actually apply a more-than-TURBO_L1-requiring frequency..
>
> Hmm, is the OPP table for SM8250 then also incorrect?
The OPP-set clock is "vcodec0_core"
The DT references VIDEO_CC_MVS0_CLK, which is a branch-child of
video_cc_mvs0_div_clk_src, so that sounds like it makes sense..
And the frequency plan concurs that.
>
> I cross-checked SM8250 and Kodiak against, msm-4.19 and msm-5.4
> correspondignly, the OPP tables are written in the same way.
>
>>
>> [...]
>>> + videocc: clock-controller@...0000 {
>>> + compatible = "qcom,sc8280xp-videocc";
>>> + reg = <0 0x0abf0000 0 0x10000>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&rpmhcc RPMH_CXO_CLK_A>,
>>> + <&sleep_clk>;
>>> + power-domains = <&rpmhpd SC8280XP_MMCX>;
>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>
>> AFAICS the PLLs will not turn on if *MX* is at < LOWSVS, but they still
>> need to be scaled 1:1 with MMCX as the freuqency rises, so you need to
>> wire up 2 power domains to the OPP table
>
> I don't see this being done for SM8250, should it also be fixed? On
> SM8550 we indeed manage MMCX and MX together. Should SC7280 also scale
> both CX and MX together?
8250 yes
On kodiak, the docs strangely say that it's *all* powered by CX, maybe
+Taniya or +Jagadeesh could confirm if that's right
Konrad
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