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Message-ID: <CAPDyKFr9pLaZRBXypf-9cZWahJOMcBc6QB-udY46GEvb0tFyNg@mail.gmail.com>
Date: Tue, 27 Jan 2026 15:27:30 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Jacky Bai <ping.bai@....com>
Cc: Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Lucas Stach <l.stach@...gutronix.de>, Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, linux-pm@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v3] pmdomain: imx: gpcv2: Fix the imx8mm gpu hang due to
wrong adb400 reset
On Fri, 23 Jan 2026 at 03:51, Jacky Bai <ping.bai@....com> wrote:
>
> On i.MX8MM, the GPUMIX, GPU2D, and GPU3D blocks share a common reset
> domain. Due to this hardware limitation, powering off/on GPU2D or GPU3D
> also triggers a reset of the GPUMIX domain, including its ADB400 port.
> However, the ADB400 interface must always be placed into power‑down mode
> before being reset.
>
> Currently the GPUMIX and GPU2D/3D power domains rely on runtime PM to
> handle dependency ordering. In some corner cases, the GPUMIX power off
> sequence is skipped, leaving the ADB400 port active when GPU2D/3D reset.
> This causes the GPUMIX ADB400 port to be reset while still active,
> leading to unpredictable bus behavior and GPU hangs.
>
> To avoid this, refine the power‑domain control logic so that the GPUMIX
> ADB400 port is explicitly powered down and powered up as part of the GPU
> power domain on/off sequence. This ensures proper ordering and prevents
> incorrect ADB400 reset.
>
> Suggested-by: Lucas Stach <l.stach@...gutronix.de>
> Signed-off-by: Jacky Bai <ping.bai@....com>
Applied for fixes and by adding a stable tag, thanks!
Kind regards
Uffe
> ---
> Changes in v3:
> - Fix the Suggested-by tag typo
> - Link to v2: https://lore.kernel.org/r/20260120-imx8mm_gpu_power_domain-v2-1-be10fd018108@nxp.com
>
> Changes in v2:
> - add prefix to patch subject as suggested by Krzysztof
> - refine the patch to move the GPUMIX ADB400 into GPU power domain
> - Link to v1: https://lore.kernel.org/r/20260119-imx8mm_gpu_power_domain-v1-0-34d81c766916@nxp.com
> ---
> drivers/pmdomain/imx/gpcv2.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pmdomain/imx/gpcv2.c b/drivers/pmdomain/imx/gpcv2.c
> index b7cea89140ee8923f32486eab953c0e1a36bf06d..a829f8da5be70d0392276bd135fb7fc1bbf10496 100644
> --- a/drivers/pmdomain/imx/gpcv2.c
> +++ b/drivers/pmdomain/imx/gpcv2.c
> @@ -165,13 +165,11 @@
> #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
> #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
>
> -#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
> -#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
> +#define IMX8MM_GPU_HSK_PWRDNACKN GENMASK(29, 27)
> #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
> #define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25)
> #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
> -#define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11)
> -#define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10))
> +#define IMX8MM_GPU_HSK_PWRDNREQN GENMASK(11, 9)
> #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8)
> #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7)
> #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
> @@ -794,8 +792,6 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
> .bits = {
> .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
> .map = IMX8MM_GPUMIX_A53_DOMAIN,
> - .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
> - .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
> },
> .pgc = BIT(IMX8MM_PGC_GPUMIX),
> .keep_clocks = true,
>
> ---
> base-commit: 0f853ca2a798ead9d24d39cad99b0966815c582a
> change-id: 20260113-imx8mm_gpu_power_domain-56c22ce012a1
>
> Best regards,
> --
> Jacky Bai <ping.bai@....com>
>
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