linux-kernel - Re: [PATCH net-next] net: phy: micrel: Add support for lan9645x internal phy

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Message-ID: <3540b83dbec35b7d2ffc370e517fe72340625dcf.camel@microchip.com>
Date: Tue, 27 Jan 2026 09:49:14 +0100
From: Jens Emil Schulz Ostergaard <jensemil.schulzostergaard@...rochip.com>
To: Andrew Lunn <andrew@...n.ch>
CC: Heiner Kallweit <hkallweit1@...il.com>, Russell King
	<linux@...linux.org.uk>, "David S. Miller" <davem@...emloft.net>, "Eric
 Dumazet" <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, "Paolo
 Abeni" <pabeni@...hat.com>, Horatiu Vultur <horatiu.vultur@...rochip.com>,
	<o.rempel@...gutronix.de>, Steen Hegelund <Steen.Hegelund@...rochip.com>,
	Daniel Machon <daniel.machon@...rochip.com>, <netdev@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next] net: phy: micrel: Add support for lan9645x
 internal phy

Hi Andrew,

On Fri, 2026-01-23 at 17:11 +0100, Andrew Lunn wrote:
> > +static int lan9645x_config_intr(struct phy_device *phydev)
> > +{
> > +     int err;
> > +
> > +     /* enable / disable interrupts */
> > +     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
> > +             /* This is an internal PHY of lan9645x and is not possible to
> > +              * change the polarity of irq sources in the OIC (CPU_INTR)
> > +              * found in lan9645x. Therefore change the polarity of the
> > +              * interrupt in the PHY from being active low instead of active
> > +              * high.
> > +              */
> > +             phy_write(phydev, LAN8804_CONTROL,
> > +                       LAN8804_CONTROL_INTR_POLARITY);
> > +
> > +             /* By default interrupt buffer is open-drain in which case the
> > +              * interrupt can be active only low. Therefore change the
> > +              * interrupt buffer to be push-pull to be able to change
> > +              * interrupt polarity.
> > +              */
> 
> It is not stated here, but i assume that there are multiple of these
> PHYs in the switch, and each PHY has its own independent connection to
> the parent interrupt controller? There is no interrupt sharing going
> on, which is common with discreet PHYs.
> 
>         Andrew

Yes you are right, there are 5 of these PHYs in the chip, each with their
on connection to the interrupt controller. It is similar to lan966x,
which has two internal PHYs of an older generation.

Thanks,
Emil