linux-kernel - Re: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <4d49c26f-3609-4a46-adbb-64cca7166721@linaro.org>
Date: Wed, 28 Jan 2026 14:53:01 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size
 properties

On 1/28/26 11:46, Konrad Dybcio wrote:
> On 1/28/26 11:33 AM, Neil Armstrong wrote:
>> Add the L1 cache size and its line size (cache-size and
>> cache-line-size) with the corresponding L1-I cache and L1-D cache.
>>
>> L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
>> L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
>> d-cache-line-size and cache-line-size of L3 cache is specified.
>>
>> All cache line sizes were confirmed by checking ccsidr_el1.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 56 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 8671c25dd68f..f8563ec79dc6 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -75,6 +75,11 @@ cpu0: cpu@0 {
>>   			compatible = "arm,cortex-a520";
>>   			reg = <0 0>;
>>   
>> +			i-cache-size = <65536>;
>> +			i-cache-line-size = <64>;
>> +			d-cache-size = <65536>;
>> +			d-cache-line-size = <64>;
>> +
>>   			clocks = <&cpufreq_hw 0>;
>>   
>>   			power-domains = <&cpu_pd0>;
>> @@ -103,11 +108,15 @@ l2_0: l2-cache {
>>   				cache-level = <2>;
>>   				cache-unified;
>>   				next-level-cache = <&l3_0>;
>> +				cache-size = <262144>;
> 
> This should be 512 kiB, shared for c0/1, according to a block
> diagram

Thanks for confirming !

Neil

> 
> Everything else lgtm, although I can't find a source for the
> cache*line* sizes
> 
> Konrad