lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <87bjidn7y2.fsf@bootlin.com>
Date: Wed, 28 Jan 2026 15:11:17 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Shiji Yang <yangshiji66@...look.com>
Cc: linux-mtd@...ts.infradead.org,  Tudor Ambarus
 <tudor.ambarus@...aro.org>,  Pratyush Yadav <pratyush@...nel.org>,
  Michael Walle <mwalle@...nel.org>,  Richard Weinberger <richard@....at>,
  Vignesh Raghavendra <vigneshr@...com>,  linux-kernel@...r.kernel.org
Subject: Re: [PATCH] mtd: spi-nor: swp: check SR_TB flag when getting tb_mask

On 28/01/2026 at 20:42:56 +08, Shiji Yang <yangshiji66@...look.com> wrote:

> When the chip does not support top/bottom block protect, the tb_mask
> must be set to 0, otherwise SR1 bit5 will be unexpectedly modified.
>
> Signed-off-by: Shiji Yang <yangshiji66@...look.com>

Good point.

Reviewed-by: Miquel Raynal <miquel.raynal@...tlin.com>

Thanks,
Miquèl

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ