| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <2403222.ElGaqSPkdT@steina-w>
Date: Wed, 28 Jan 2026 15:55:27 +0100
From: Alexander Stein <alexander.stein@...tq-group.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Chen-Yu Tsai <wenst@...omium.org>, Chia-I Wu <olvaffe@...il.com>,
Dong Aisheng <aisheng.dong@....com>, Laura Nao <laura.nao@...labora.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Nícolas F. R. A. Prado <nfraprado@...labora.com>,
Yassine Oudjana <y.oudjana@...tonmail.com>, Stephen Boyd <sboyd@...nel.org>,
Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Cc: kernel@...labora.com, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject:
Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Hi Nicolas,
Am Mittwoch, 28. Januar 2026, 15:11:33 CET schrieb Nicolas Frattaroli:
> On Tuesday, 27 January 2026 15:55:29 Central European Standard Time Alexander Stein wrote:
> > Hello,
> >
> > Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd:
> > > Quoting Nicolas Frattaroli (2025-12-15 03:23:58)
> > > > When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
> > > > operations, such as setting the rate or switching parents. However,
> > > > another operation that can and often does touch actual hardware state is
> > > > recalc_rate, which may also be affected by such a dependency.
> > > >
> > > > Add parent enables/disables where the recalc_rate op is called directly.
> > > >
> > > > Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
> > > > Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
> > > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> > > > Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
> > > > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
> > > > ---
> > >
> > > Applied to clk-next
> >
> > Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126.
> > Last lines on bootlog (earlycon is necessary)
> > > [ 1.175639] Initialise system trusted keyrings
> > > [ 1.178907] workingset: timestamp_bits=42 max_order=19 bucket_order=0
> > > [ 1.185822] NFS: Registering the id_resolver key type
> > > [ 1.190295] Key type id_resolver registered
> > > [ 1.194473] Key type id_legacy registered
> > > [ 1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
> > > [ 1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver
> > > Registering... [ 1.213235] cryptd: max_cpu_qlen set to 1000
> > > [ 1.274689] Key type asymmetric registered
> > > [ 1.275939] Asymmetric key parser 'x509' registered
> > > [ 1.280896] Block layer SCSI generic (bsg) driver version 0.4 loaded
> > > (major 242) [ 1.288278] io scheduler mq-deadline registered
> > > [ 1.292840] io scheduler kyber registered
> > > [ 1.299245] ledtrig-cpu: registered to indicate activity on CPUs
> >
> > Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the problem.
>
> Hi Alexander,
>
> sorry for breaking -next.
>
> Can you try the following patch to print which clock+parent is causing
> the hang on your platform?
>
> ---
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 1b0f9d567f48..fa1443517768 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *core,
> unsigned long rate = parent_rate;
>
> if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: enabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_prepare_enable(core->parent);
> + }
>
> rate = core->ops->recalc_rate(core->hw, parent_rate);
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: disabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_disable_unprepare(core->parent);
> + }
>
> clk_pm_runtime_put(core);
> }
> @@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core)
> */
> clk_core_update_duty_cycle_nolock(core);
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: enabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_prepare_enable(core->parent);
> + }
>
> /*
> * Set clk's rate. The preferred method is to use .recalc_rate. For
> @@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core)
> rate = 0;
> core->rate = core->req_rate = rate;
>
> - if (core->flags & CLK_OPS_PARENT_ENABLE)
> + if (core->flags & CLK_OPS_PARENT_ENABLE) {
> + pr_info("%s: disabling parent %s for %s\n", __func__,
> + core->parent ? core->parent->name : "(null)",
> + core->name);
> clk_core_disable_unprepare(core->parent);
> + }
>
> /*
> * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
> ---
>
> Thanks for reporting this.
thanks for the debugging patch. I'll respond to the other thread where
Mark is active as well.
Best regards,
Alexander
> Kind regards,
> Nicolas Frattaroli
>
> >
> > Best regards,
> > Alexander
> >
>
>
>
>
>
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
Powered by blists - more mailing lists