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Message-ID: <5050249.GXAFRqVoOG@steina-w>
Date: Wed, 28 Jan 2026 15:55:54 +0100
From: Alexander Stein <alexander.stein@...tq-group.com>
To: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>,
Mark Brown <broonie@...nel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Dong Aisheng <aisheng.dong@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Yassine Oudjana <y.oudjana@...tonmail.com>,
Laura Nao <laura.nao@...labora.com>,
Nícolas F. R. A. Prado <nfraprado@...labora.com>,
Chia-I Wu <olvaffe@...il.com>, Chen-Yu Tsai <wenst@...omium.org>,
kernel@...labora.com, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Hi everyone,
Am Mittwoch, 28. Januar 2026, 15:47:08 CET schrieb Mark Brown:
> On Wed, Jan 28, 2026 at 03:09:46PM +0100, Nicolas Frattaroli wrote:
> > On Wednesday, 28 January 2026 00:14:29 Central European Standard Time Mark Brown wrote:
>
> > > Do you have a debugging patch we could run which would say which clocks
> > > are impacted? I guess it's more of an issue for the platforms that give
> > > no output but for at least Avenger96 I was getting earlycon output.
>
> > Try this one
>
> For the Avenger96 that says:
>
> [ 0.347816] __clk_core_init: enabling parent ck_hse for ck_per
> [ 0.352230] __clk_core_init: disabling parent ck_hse for ck_per
> [ 0.358207] __clk_core_init: enabling parent pll1_p for ck_mpu
> [ 0.364005] __clk_core_init: disabling parent pll1_p for ck_mpu
>
> https://lava.sirena.org.uk/scheduler/job/2412562#L563
>
This is for TQMa8MPxL/MBa8MPxL:
[ 1.452788] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
[ 1.457677] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
[ 1.464270] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
[ 1.471760] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
[ 1.478360] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
[ 1.485259] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div
Best regards,
Alexander
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