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Message-Id: <20260128-gs101-pd-v4-6-cbe7bd5a4060@linaro.org>
Date: Wed, 28 Jan 2026 16:10:55 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Alim Akhtar <alim.akhtar@...sung.com>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>, Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>
Cc: Peter Griffin <peter.griffin@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>, Juan Yescas <jyescas@...gle.com>,
Will McVicker <willmcvicker@...gle.com>, kernel-team@...roid.com,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org,
André Draszik <andre.draszik@...aro.org>,
Marek Szyprowski <m.szyprowski@...sung.com>
Subject: [PATCH v4 06/10] pmdomain: samsung: don't hard-code offset for
registers to 0 and 4
On platforms such as Google gs101, direct mmio register access to the
PMU registers doesn't necessarily work and access must happen via a
regmap created by the PMU driver instead.
When such a regmap is used it will cover the complete PMU memory region
rather than individual power domains. This means the register offsets
for the configuration and status registers will have to take the power
domain offsets into account, rather than unconditionally hard-coding 0
and 4 respectively.
Update the code to allow that.
Tested-by: Marek Szyprowski <m.szyprowski@...sung.com>
Signed-off-by: André Draszik <andre.draszik@...aro.org>
---
drivers/pmdomain/samsung/exynos-pm-domains.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomain/samsung/exynos-pm-domains.c
index 3bcba7d38ac1572ef4bc2f4052c904dd6c4a7bfd..8df46b41f9bc8f0b2a03300169a4b52457faaf4d 100644
--- a/drivers/pmdomain/samsung/exynos-pm-domains.c
+++ b/drivers/pmdomain/samsung/exynos-pm-domains.c
@@ -30,6 +30,8 @@ struct exynos_pm_domain {
struct regmap *regmap;
struct generic_pm_domain pd;
u32 local_pwr_cfg;
+ u32 configuration_reg;
+ u32 status_reg;
};
static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -41,7 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
pwr = power_on ? pd->local_pwr_cfg : 0;
- err = regmap_write(pd->regmap, 0, pwr);
+ err = regmap_write(pd->regmap, pd->configuration_reg, pwr);
if (err) {
pr_err("Regmap write for power domain %s %sable failed: %d\n",
domain->name, power_on ? "en" : "dis", err);
@@ -53,7 +55,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
while (timeout-- > 0) {
unsigned int val;
- err = regmap_read(pd->regmap, 0x4, &val);
+ err = regmap_read(pd->regmap, pd->status_reg, &val);
if (err || ((val & pd->local_pwr_cfg) != pwr)) {
cpu_relax();
usleep_range(80, 100);
@@ -164,6 +166,8 @@ static int exynos_pd_probe(struct platform_device *pdev)
pd->pd.power_off = exynos_pd_power_off;
pd->pd.power_on = exynos_pd_power_on;
pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
+ pd->configuration_reg += 0;
+ pd->status_reg += 4;
/*
* Some Samsung platforms with bootloaders turning on the splash-screen
@@ -174,7 +178,7 @@ static int exynos_pd_probe(struct platform_device *pdev)
of_device_is_compatible(np, "samsung,exynos4210-pd"))
exynos_pd_power_off(&pd->pd);
- ret = regmap_read(pd->regmap, 0x4, &val);
+ ret = regmap_read(pd->regmap, pd->status_reg, &val);
if (ret)
return dev_err_probe(dev, ret, "failed to read status");
--
2.52.0.457.g6b5491de43-goog
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