linux-kernel - Re: [PATCH 0/2] Fix a __clk_core

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Message-ID: <a4f87b4b-efce-4c8c-a523-69949935a096@sirena.org.uk>
Date: Wed, 28 Jan 2026 20:17:09 +0000
From: Mark Brown <broonie@...nel.org>
To: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Cc: Alexander Stein <alexander.stein@...tq-group.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	Chen-Yu Tsai <wenst@...omium.org>, Abel Vesa <abelvesa@...nel.org>,
	Peng Fan <peng.fan@....com>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>, linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org, kernel@...labora.com,
	imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 0/2] Fix a __clk_core_init parental issue

On Wed, Jan 28, 2026 at 07:38:49PM +0100, Nicolas Frattaroli wrote:
> Mark and Alexander, please test to see if these patches resolve the
> issues on your boards.
> 
> I expect the first patch to completely fix the problem on the Avenger96
> (STM32MP1) board.

This gets further but still fails on Avenger96, looks like we've got
more clocks need work:

[    0.513739] __clk_core_init: enabling parent pll3_q for spi1_k
[    0.519521] __clk_core_init: disabling parent pll3_q for spi1_k
[    0.525489] __clk_core_init: enabling parent pll3_q for spi2_k
[    0.531311] __clk_core_init: disabling parent pll3_q for spi2_k
[    0.537275] __clk_core_init: enabling parent pll3_q for spi3_k
[    0.543101] __clk_core_init: disabling parent pll3_q for spi3_k
[    0.549066] __clk_core_init: enabling parent ck_hsi for spi4_k
[    0.554894] __clk_core_init: disabling parent ck�
U-Boot SPL 2023.07.02-dh-stm32mp1-dhcor-avenger96-20230727.02 (Jul 11 2023 - 15:20:44 +0000)

   https://lava.sirena.org.uk/scheduler/job/2413747#L593

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