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Message-ID: <919c7a9a-8341-4329-9fcc-630a2a3d0b91@sirena.org.uk>
Date: Wed, 28 Jan 2026 20:41:18 +0000
From: Mark Brown <broonie@...nel.org>
To: "Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Vaishnav Achath <vaishnav.a@...com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Hervé Codina <herve.codina@...tlin.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Vignesh Raghavendra <vigneshr@...com>,
Santhosh Kumar K <s-k6@...com>,
Pratyush Yadav <pratyush@...nel.org>,
Pascal Eberhard <pascal.eberhard@...com>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v4 10/15] spi: cadence-qspi: Kill cqspi_jh7110_clk_init
On Thu, Jan 22, 2026 at 04:13:35PM +0100, Miquel Raynal (Schneider Electric) wrote:
> This controller can be fed by either a main "ref" clock, or three clocks
> ("ref" again, "ahb", "apb"). In practice, it is likely that all
> controllers have the same inputs, but a single clock feeds the three
> interfaces (ref is used for controlling the external interface, ahb/apb
> the internal ones). Handling these clocks is in no way SoC specific,
> only the number of expected clocks may change. Plus, we will soon be
> adding another controller requiring an AHB and an APB clock as well, so
> it is time to align the whole clock handling.
This also fails to apply:
Applying: spi: cadence-qspi: Kill cqspi_jh7110_clk_init
error: patch failed: drivers/spi/spi-cadence-quadspi.c:1829
error: drivers/spi/spi-cadence-quadspi.c: patch does not apply
Patch failed at 0009 spi: cadence-qspi: Kill cqspi_jh7110_clk_init
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