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Message-ID: <20260128-nacho-craziness-45a3e575ba7c@spud>
Date: Wed, 28 Jan 2026 20:50:33 +0000
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org
Cc: conor@...nel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1] riscv: dts: microchip: add can resets to mpfs
From: Conor Dooley <conor.dooley@...rochip.com>
The can IP on PolarFire SoC requires the use of the blocks reset
during normal operation, and the property is therefore required by the
binding, causing a warning on the m100pfsevp board where it is default
enabled:
mpfs-m100pfsevp.dtb: can@...0c000 (microchip,mpfs-can): 'resets' is a required property
Add the reset to both can nodes.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
CC: Conor Dooley <conor.dooley@...rochip.com>
CC: Daire McNamara <daire.mcnamara@...rochip.com>
CC: Rob Herring <robh@...nel.org>
CC: Krzysztof Kozlowski <krzk+dt@...nel.org>
CC: linux-riscv@...ts.infradead.org
CC: devicetree@...r.kernel.org
CC: linux-kernel@...r.kernel.org
arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 5c2963e269b8..a0ffedc2d344 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -428,6 +428,7 @@ can0: can@...0c000 {
clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
+ resets = <&mss_top_sysreg CLK_CAN0>;
status = "disabled";
};
@@ -437,6 +438,7 @@ can1: can@...0d000 {
clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
+ resets = <&mss_top_sysreg CLK_CAN1>;
status = "disabled";
};
--
2.51.0
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